7733 datasheet(498/940 Pages) RENESAS

498 / 940 page

7733 Group User’s Manual

18–32

LOW VOLTAGE VERSION

18.6 Applications

Some application examples of connecting external memorys for the low voltage version are described

bellow.

Applications shown here are just examples. Modify the desired application to suit the user’s need and make

sufficient evaluation before actually using it.

18.6.1 Memory expansion

The following items of the low voltage version are the same as section “17.1 Memory expansion,” but

a part of the calculation way and constants for parameters is different:

•Memory expansion model

•Calculation way for address access time of external memory

•Bus timing

•Memory expansion way

Address access time of external memory ta(AD)

ta(AD) = td(A-E) + tw(EL) – tsu(D-E) – (address decode timeV1 + address latch delay timeV2)

address decode timeV1 : time necessary for validating a chip select signal after an address is decoded

address latch delay timeV2 : delay time necessary for latching an address

(This is not necessary on the minimum model.)

Data setup time of external memory for writing data tsu(D)

tsu(D) = tw(EL) – td(E–DQ)

Table 18.6.1 lists the calculation formulas and constants for each parameter of the low voltage version.

Figure 18.6.1 shows the relationship between ta(AD) and 2!

f(f2). Figure 18.6.2 shows the relationship

between tsu(D) and 2!

f(f2).

Table 18.6.1 Calculation formulas and constants for each parameter (Unit : ns)

Wait 1

Wait 0

– 30

– 88

– 35

– 63

– 35

No wait

0 or 1

3 ! 109

f(f2)

4 ! 109

f(f2)

2 ! 109

f(f2)

1 ! 109

f(f2)

1 ! 109

f(f2)

Wait bit : Bit 2 at address 5E16

Wait selection bit : Bit 0 at address 5F16

Note: This is applied to the case where the system clock selection bit (bit 3 at address 6C16) = “0.”

Software wait

Wait bit

Wait selection bit

td(A-E)

tw(EL)

tsu(D-E)

tsu(E-DQ)

tpxz(E-DZ)

tpzx(E-DZ)

18.6 Applications

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