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7733 Datasheet(PDF) 499 Page - Renesas Technology Corp |
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7733 Datasheet(HTML) 499 Page - Renesas Technology Corp |
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499 / 940 page ![]() 7733 Group User’s Manual LOW VOLTAGE VERSION 18–33 Fig. 18.6.1 Relationship between ta(AD) and 2! f(f2) Fig. 18.6.2 Relationship between tsu(D) and 2! f(f2) 2 3 4 5 6 7 8 9 10 11 12 0 200 400 600 800 1000 1200 1400 1600 1800 2000 1875 1208 875 675 541 446 375 319 275 238 208 875 541 375 275 208 160 125 75 56 41 No wait Wait 1 or Wait 0 is valid. 97 External clock input frequency 2!f(f2) [MHz] [ns] 2 3 4 5 6 7 8 9 10 11 12 0 500 1000 1500 2000 2500 3000 3500 3297 2130 1547 1197 963 797 672 574 497 433 380 2322 1488 1072 822 655 536 447 377 322 276 238 822 572 422 322 250 197 155 122 94 72 No wait Wait 1 is valid. Wait 0 is valid. 1322 [ns] External clock input frequency 2!f(f2) [MHz] V Address decode time and address latch delay time are not considered. 18.6 Applications |
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