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7733 Datasheet(PDF) 544 Page - Renesas Technology Corp |
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7733 Datasheet(HTML) 544 Page - Renesas Technology Corp |
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544 / 940 page  EXTERNAL ROM VERSION 7733 Group User’s Manual 20–28 20.8 Reset Fig. 20.8.2 State of SFR area and internal RAM area immediately after reset (4) 7A16 7B16 7C16 7D16 7E16 0 RO UART1 receive interrupt control register 6016 6116 6216 6316 6416 6516 6616 6716 6816 6916 7016 7116 7216 7316 7416 7516 7616 7716 7816 7916 7F16 6B16 6C16 6D16 6E16 6F16 6A16 Address Oscillation circuit control register 0 Serial transmit control register A-D / UART 2 trans./rece. interrupt control register UART0 transmission interrupt control register UART1 transmission interrupt control register INT2/Key input interrupt control register Watchdog timer frequency selection flag Register name Watchdog timer register Timer A0 interrupt control register Timer A2 interrupt control register Timer A3 interrupt control register Timer A4 interrupt control register Timer B1 interrupt control register Timer B2 interrupt control register INT0 interrupt control register Access characteristics RW(g2) RW RW RW RW b7 b0 WO RW RW RW RW RW RW RW RW RW RW State immediately after reset ? ? ? ? ? 0 00 0 ? 0 ? (g1) b7 b0 ? 0 0 0 0 0 00 0 00 00 00 0 00 0 Port function control register UART0 receive interrupt control register Timer A1 interrupt control register Timer B0 interrupt control register INT1 interrupt control register RW RW WO RW RW RW 00 0 0 0 1 00 0 0 00 0 0 00 0 0 00 0 0 00 0 0 00 0 ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 00 0 0 0 0 0 0 00 0 0 00 0 0 00 0 ? ? ? 00 0 00 0 00 0 00 0 A value of “FFF16” is set to the watchdog timer. (Refer to Chapter “10. WATCHDOG TIMER.”) For access characteristics at address 6C 16, also refer to Figure 14.3.2. The contents of addresses 6216 and 6316 of the M37733S4BFP differ from those of the M37733MHBXXXFP. Do not wirte to address 6316. sInternal RAM area (M37733S4BFP: addresses 80 16 to FFF16) qAt hardware reset (not including the case where the stop or wait mode is terminated)...Undefined. qAt software reset...Retains the state immediately before reset . qWhen the stop or wait mode is terminated (when hardware reset is used)...Retains the state immediately before the STP or WIT instruction is executed. ? RW g 3 00 0 g1 g2 g3 g4 Waveform output mode register g3 (Reserved area) g4 UART 2 transmit/receive mode register UART 2 baud rate register (BRG2) UART 2 transmission buffer register UART 2 transmit/receive control register 0 UART 2 transmit/receive control register 1 UART 2 receive buffer register Oscillation circuit control register 1 00 RW ? 00 0 00 0 0 WO WO WO RW RO 1 00 0 RW RW RO RO 00 0 0 00 1 0 RO 00 0 00 0 ? RW ? ? 0 00 0 0 00 0 ? 0 RW RW RW 0 ? 0 00 ? |
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