7733 datasheet(685/940 Pages) RENESAS

685 / 940 page

CONNECTING EXTERNAL DEVICES

7735 Group User’s Manual

12–9

Table 12.1.3 Method to select whether to output or stop clock

φ1

Clock

φ1 output

Clock

φ1 stopped

Remark

Processor mode

Single-chip or Memory expansion mode

Microprocessor mode

Clear the signal output disable

selection bit*2 to “0.”

Set the signal output disable

selection bit to “1.” (Note)

Clock

φ1 is output after reset.

The clock

φ1 output selection bit is

ignored.

Set the clock

φ1 output selection bit*1 to

“1.”

Clear the clock

φ1 output selection bit to

“0.” (Pin P42 functions as a programmable

I/O port.)

Clock

φ1 is stopped after reset.

The signal output disable selection bit is

ignored.

Clock

φ1 output selection bit*1: Bit 7 at address 5E16

Signal output disable selection bit*2: Bit 6 at address 6C16 (Refer to Table 12.1.4.)

Note: When bit 2 at address C16 (Port P4 direction register) is set to “1,” bit 2 of the port P4 register is

output.

Table 12.1.4 Functions of signal output disable bit

Processor

mode

Conditions

Signal output disable selection bit

Memory

expansion or

Microprocessor

mode

Signals

____

RDE,

____

WEL,

____

WEH

____

RDE,

____

WEL,

____

WEH

____

RDE,

____

WEL,

____

WEH

Clock

φ1

When the external area is accessed

When the internal area is accessed

When the standby state selection

bit = “1” in the stop or wait mode

When the standby state selection

bit = “0” in the stop or wait mode

Operating

Stopped at “H” level

Stopped at “L” level

Stopped at “H” level

Stopped (Output levels can be set.)

(Refer to Figures 11.3.1 and 11.4.1.)

Stopped (Note)

Microprocessor

mode

Enable signal

When not in the stop or wait mode

Single-chip

mode

When in the stop or wait mode

Operating

Stopped at “H” level

Stopped at “L” level

g All functions listed in Table 12.1.4 are not emulated by a debugger.

g For the stop and wait modes and the standby state selection bit, refer to chapter “11. STOP AND WAIT

MODES.”

Note: When bit 2 at address C16 (Port direction register) is set to “1,” bit 2 of the port P4 register is output.

:Not affected by the signal output disable selection bit.

Each signal’s state

Operating (independent

of the

φ1 output selection

bit)

12.1 Signals required for accessing external devices

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