7733 datasheet(684/940 Pages) RENESAS

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CONNECTING EXTERNAL DEVICES

7735 Group User’s Manual

12–8

12.1.2 External data bus width selection signal (Pin BYTE’s level)

This signal is used to select the external data bus width from 8 bits and 16 bits. When this signal level

is “L,” the external data bus is 16 bits wide; when this signal level is “H,” the external data bus is 8 bits

wide. (Refer to Table 12.1.1.) This signal level must be fixed to either “H” or “L.”

This signal is valid only for the external areas. (When the internal area is accessed, the data bus is always

16 bits wide.)

____

12.1.3 Read enable signal (RDE) and Write enable signals (WEL, WEH)

These signals are output when data is read or written from or to the external area. When the internal area

is accessed, these signals are stopped at “H” level by setting the signal output disable selection bit (bit 6

at address 6C16) to “1.” (Refer to Table 12.1.4.)

Table 12.1.2 Functions of read enable signal and write enable signals

External data bus state

Data is read out.

1-byte data is written to even address.

1-byte data is written to odd address.

1-word data is written.

Data is read out.

Data is written.

External data bus width

16 bits

(BYTE = “L”)

8 bits

(BYTE = “H”)

____

RDE

____

WEL

____

WEH

12.1.4 Address latch enable signal (ALE)

This signal is used to latch an address from a multiplexed signal. This multiplexed signal consists of the

address and data and is input or output to or from pins A0/D0 to A15/D15, A16/D0 to A23/D7. When this signal

level is “H,” take the address into a latch and output it simultaneously. When this signal level is “L,” retain

the latched address.

____

_____

12.1.5 Signals related to ready function (RDY, RSMP)

These signals are required to use the ready function. (Refer to section “12.3 Ready function.”)

_____

12.1.6 Signals related to hold function (HOLD, HLDA)

These signals are required to use the hold function. (Refer to section “12.4 Hold function.”)

12.1.7 Clock

φ1

This signal has the same period as internal clock

φ.

Whether clock

φ1 is output or stopped can be selected by software. However, the method of this selection

depends on the processor mode. Table 12.1.3 lists the method to select whether to output or stop clock

φ1. Figure 12.1.4 shows the clock φ1 output start timing.

12.1 Signals required for accessing external devices

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