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7733 Datasheet(PDF) 705 Page - Renesas Technology Corp |
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7733 Datasheet(HTML) 705 Page - Renesas Technology Corp |
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705 / 940 page  CONNECTING EXTERNAL DEVICES 7735 Group User’s Manual 12–29 When “L” level which is input to pin HOLD is the accepted, the address which was output immediately before is output again, instead of a new address. Sampling is not performed until 16-bit data input/output is finished. ( “L” level which is input to pin HOLD is not accepted.) External address bus/ External data bus ALE HLDA HOLD Address 1 ! 1 1 ! 1 Hold state Not sampled External data bus Data length External data bus width Software wait 16 8 16 (When accessed starting from even address) No wait In use q State when “L” level is input to pin HOLD Sampling timing Bus is in use. <<When “L” level is input to pin HOLD while bus is in use (4)>> External address bus Clock 1 Data High-order address Floating Floating Floating Bus is in use. BHE Data Low-order address g CS0 to CS4 g RDE, WEL, WEH Bus is not in use. Fig. 12.4.6 Timing when hold state is accepted and terminated (5) 12.4 Hold function |
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