7733 datasheet(731/940 Pages) RENESAS

731 / 940 page

APPLICATIONS

7735 Group User’s Manual

17–5

Fig. 17.1.1 Bus timing diagrams

ALE

High-order address

td(An-RDE)

tsu(A-ALE)

td(ALE-RDE)

tsu(D-RDE)

tw(RDE)

Port P0

(A16, A17)

Port P1

(A8 to A15)

Port P2

(A0/D0 to A7/D7)

Data

td(WE-DQ)

High-order address

tw(ALE)

ta(AD)

tsu(D)

RDE

WEL, WEH

tw(WE)

CS4 to CS0

td(CS-RDE)

td(CS-WE)

Data (odd address)

ALE

Low-order

address

High-order address

td(An-RDE)

tsu(A-ALE)

td(ALE-RDE)

tsu(D-RDE)

tw(RDE)

Port P0

(A16, A17)

Port P2

(A0/D0 to A7/D7)

Data (even address)

td(WE-DQ)

High-order address

tw(ALE)

ta(AD)

tsu(D)

RDE

WEL, WEH

tw(WE)

CS4 to CS0

td(CS-RDE)

td(CS-WE)

Port P1

(A8/D8 to A15/D15)

tsu(D-RDE)

td(WE-DQ)

External memory’s

output data

When BYTE = “L” (External data bus = 16 bits wide)

When BYTE = “H” (External data bus = 8 bits wide)

: Specifications of the 7735 Group

(The others are specifications of external

memory.)

When data is written

When data is read

Middle-order

address

Middle-order

address

When data is written

When data is read

External memory’s

output data

Low-order

address

Low-order

address

Low-order

address

Middle-order address

External memory’s

output data

17.1 Memory expansion

7733 Datasheet(PDF) 731 Page - Renesas Technology Corp

7733 Datasheet(HTML) 731 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL