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7733 Datasheet(PDF) 732 Page - Renesas Technology Corp |
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7733 Datasheet(HTML) 732 Page - Renesas Technology Corp |
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732 / 940 page ![]() APPLICATIONS 7735 Group User’s Manual 17–6 Figure 17.1.2 shows the relationship between ta(AD), tsu(D) and the system clock frequency. For ta(AD) in Figure 17.1.2, an address decode time and an address latch delay time are not considered. The actual ta(AD) is a value obtained by subtracting the above times from the value shown in Fig.17.1.2. [MHz] [ns] 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 0 100 200 300 400 500 175 147 91 496 425 369 325 288 258 232 210 191 175 160 147 135 125 115 106 98 91 85 210 125 106 78 67 58 50 42 36 30 25 20 15 11 8 5 [ MHz] [ns] 7 8 9 591 10 11 12 13 14 15 16 17 18 19 20 21 135 22 125 23 24 25 0 100 200 283 300 400 500 600 700 766 800 900 1000 668 527 241 47 4 180 158 138 463 533 408 362 241 208 891 429 391 357 328 302 279 259 224 209 195 182 171 622 324 292 265 241 220 202 185 171 158 146 116 108 336 122 108 95 84 74 65 58 50 44 38 33 28 No wait Wait 1 is valid. Wait 0 is valid. System clock (Main clock) frequency f(XIN) g Address decode time and address latch delay time are not considered. No wait System clock (Main clock) frequency f(XIN) Wait 1 or Wait 0 is valid. Fig. 17.1.2 Relationship between ta(AD), tsu(D) and f(XIN) 17.1 Memory expansion |
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