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7733 Datasheet(PDF) 736 Page - Renesas Technology Corp

Part # 7733
Description  16-BIT SINGLE-CHIP MICROCOMPUTER
PDF  940 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

7733 Datasheet(HTML) 736 Page - Renesas Technology Corp

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APPLICATIONS
7735 Group User’s Manual
17–10
(3) Precautions on memory expansion
When specifications of the 7735 Group do not match those of an external memory as described in
the following Œ to Ž, some considerations about the circuit are necessary:
Œ When using an external memory which requires a long address access time (ta(AD))
 When using an external memory which outputs data within an interval of tpxz(RDE-DZ) after signal
____
RDE’s
falling edge
Ž When using an external memory which outputs data for more than an interval of tpzx(RDE-DZ)
____
after signal RDE’s rising edge
Œ When using an external memory which requires a long address access time (ta(AD))
When an external memory requires a long address access time (ta(AD)) which does not satisfy the
7735 Group’s tsu(D-RDE), try to lower f(XIN) or extend a bus cycle by inserting a wait.
There are two methods for insertion of a wait: the software wait and the ready function. For the
software wait, refer to section “12.2 Software wait”; for the ready function, refer to section “12.3
Ready function.”
q Wait 1 (Software wait)
____ ____
____
Insert a wait equivalent to one cycle of clock
φ1 while signal RDE/WEL/WEH is at “L”-level.
q Wait 0 (Software wait)
____ ____
____
Insert a wait equivalent to one cycle of clock
φ1 while signal RDE/WEL/WEH is at “H”- and “L”-
levels.
q Ready function
Insert a wait in an arbitrary duration.
Figure 17.1.5 shows a ready generating circuit example (with no wait). In Figure 17.1.5, when
____
f(XIN) > 20.7 MHz, the setup time for the RDY input (tsu(RDY-
φ1)) is insufficient. In this case, refer to
the ready generating circuit example (with wait 1) shown in Figure 17.1.6. In Figure 17.1.6,
tsu(RDY-
φ1) is satisfied when f(XIN)
≤ 25 MHz. Note that a wait generated by the ready function is also
valid for the access to the internal area. Therefore, in Figures 17.1.5 and 17.1.6, areas where the wait
_____
is inserted are specified by using signals RSMP and CS0.
For circuits where the software wait is used, refer to Figures 17.1.2 to 17.1.5.
17.1 Memory expansion



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