7733 datasheet(761/940 Pages) RENESAS

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LOW VOLTAGE VERSION

7735 Group User’s Manual

18-13

18.6 Applications

Some application examples of connecting external memorys for the low voltage version are described below.

For the basic description of the memory expansion, refer to chapter “17. APPLICATIONS.”

Applications shown here are just examples. Modify the desired application to suit the user’s need and make

sufficient evaluations before actually using it.

18.6.1 Memory expansion

The following items of the 7735 Group’s low voltage version are the same as section “17.1 Memory

expansion” in part 1, but a part of the caluculation way and constants for each parameter is different:

•Memory expansion model

•Caluculation way for address access time of external memory

•Bus timing

•Memory expansion way

Address access time of external memory ta(AD)

ta(AD) = td(A-RDE) + tw(RDE) – tsu(D-RDE) – (address decode timeV1 + address latch delay timeV2)

address decode timeV1

: time necessary for validating a chip select signal after an address is decoded

address latch delay timeV2 : time necessary for latching an address

Data setup time of external memory for writing data tsu(D)

tsu(D) = tw(WE) – td(WE–DQ)

Table 18.6.1 lists the caluculation formulas and constants for each parameter of the low voltage version.

Figure 18.6.1 shows the relationship between ta(AD) and 2• f(f2). Figure 18.6.2 shows the relationship

between tsu(D) and 2• f(f2).

Table 18.6.1 Caluculation formulas and constants for each parameter (Unit : ns)

Wait 1

Wait 0

No wait

0 or 1

4 ! 109

2• f(f2)

Wait bit : Bit 2 at address 5E16

Wait selection bit : Bit 0 at address 5F16

Note: This is applied to the case where the system clock selection bit (bit 3 at address 6C16) = “0.”

– 63

– 38

– 35

–38

– 88

3 ! 109

2• f(f2)

1 ! 109

2• f(f2)

Software wait

Wait bit

Wait selection bit

td(A-RDE)

tw(RDE)

tw(WE)

tsu(D-RDE)

td(WE-DQ)

2 ! 109

2• f(f2)

2 !109

2• f(f2)

4 ! 109

2• f(f2)

18.6 Applications

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