7733 datasheet(757/940 Pages) RENESAS

757 / 940 page

LOW VOLTAGE VERSION

7735 Group User’s Manual

18-9

Symbol

td(CS–WE)

td(CS–RDE)

th(WE–CS)

th(RDE–CS)

td(An–WE)

td(An–RDE)

td(A–WE)

td(A–RDE)

th(WE–An)

th(RDE–An)

tw(ALE)

tsu(A–ALE)

th(ALE–A)

td(ALE–WE)

td(ALE–RDE)

td(WE–DQ)

th(WE–DQ)

tw(WE)

tpxz(RDE–DZ)

tpzx(RDE–DZ)

tw(RDE)

td(RSMP–WE)

td(RSMP–RDE)

th(

φ 1–RSMP)

td(WE–

φ 1)

td(RDE–

φ 1)

td(

φ 1–HLDA)

1 ! 109

2• f(f2)

4 ! 109

2• f(f2)

1 ! 109

2• f(f2)

18.4.9 Memory expansion mode and Microprocessor mode : with wait 1

Timing requirements (Vcc = 2.7 to 5.5 V, Vss = 0 V, Ta = –40 to 85

°C, f(XIN) = 12 MHz (Note 1), unless

otherwise noted)

g The rise/fall time of an input signal must be 100 ns or less, unless otherwise noted.

Switching characteristics (Vcc = 2.7 to 5.5 V, Vss = 0 V, Ta = –40 to 85

°C, f(XIN) = 12 MHz, unless

otherwise noted)

Unit

Limits

Data formula (Min.)

1 ! 109

2• f(f2)

1 ! 109

2• f(f2)

1 ! 109

2• f(f2)

1 ! 109

2• f(f2)

1 ! 109

2• f(f2)

1 ! 109

2• f(f2)

tw(H)

tw(L)

tsu(D–RDE)

th(RDE–D)

Min.

Limits

Unit

External clock input cycle time (Note 2)

External clock input high-level pulse width (Note 3)

External clock input low-level pulse width (Note 3)

External clock rise time

External clock fall time

Data input setup time

Data input hold time

Parameter

Max.

Symbol

Notes 1: This is applied when the main clock division selection bit = “0” and f(f2) = 6 MHz.

2: When the main clock division selection bit = “1,” the minimum value of tc = 166 ns.

3: When the main clock division selection bit = “1,” values of tw(H)/tc and tw(L)/tc must be set to values

from 0.45 through 0.55.

Parameter

Chip-select output delay time

Chip-select hold time

Address output delay time

Address hold time

ALE pulse width

Address output setup time

Address hold time

ALE output delay time

Data output delay time

Data hold time

____

WEL, WEH

pulse width

Floating start delay time

Floating release delay time

____

RDE

pulse width

_____

RSMP

output delay time

_____

RSMP

hold time

φ 1 output delay time

_____

HLDA

output delay time

120

1 ! 109

2• f(f2)

4 ! 109

2• f(f2)

Note: f(f2) represents the clock f2 frequency.

For the relationship with the main clock and sub clock, refer to Table 14.3.1 in part 1.

– 43

– 35

– 30

– 38

– 58

– 63

– 43

– 73

Conditions

Fig. 18.4.1

Max.

Min.

298

295

18.4 Electrical characteristics

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