7733 datasheet(813/940 Pages) RENESAS

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OVERVIEW

7736 Group User’s Manual

1–9

(2) In memory expansion mode (External bus mode A)

Table 1.3.6 Examples of handling unused pins in memory expansion mode (External bus mode A)

Pins

P42–P47, P5–P8, P10

(Note 7)

_____

BHE (Note 3), ALE (Note 4), HLDA

XOUT (Note 6)

_____

____

HOLD

, RDY

AVcc

AVss, VREF

EVL0, EVL1

Handling example

Connect these pins to pin Vcc or Vss via resistors after these

pins are set to the input mode, or leave these pins after they are

set to the output mode (Notes 1 and 2).

Leave these pins open after writing data to the port P9 register (Note 8).

Leave these pins open. (Note 5)

Leave this pin open.

Connect these pins to pin Vcc via resistors after these pins are

set to the input mode. (These pins are pulled high.) (Note 2)

Connect this pin to pin Vcc.

Connect these pins to pin Vss.

Leave these pins open.

Fig. 1.3.2 Examples of handling unused pins in memory expansion mode (External bus mode A)

Notes 1: When leaving these pins open after they are set to the output mode, note the following: these pins

function as input ports from reset until they are switched to the output mode by software. Therefore,

voltage levels of these pins are undefined and the power source current may increase while these

pins function as input ports. Software reliability can be enhanced when the contents of the above

ports’ direction registers are set periodically. This is because these contents may be changed by

noise, a program runaway which occurs owing to noise, etc.

2: For unused pins, use the shortest possible wiring (within 20 mm from the microcomputer’s pins).

3: This is applied when “H” level is input to pin BYTE.

4: This is applied when “H” level is input to pin BYTE and the accessible area has a capacity of 64 Kbytes.

5: When Vss level is applied to pin CNVss, note the following: these pins function as input ports from

reset until the processor mode is switched to the memory expansion mode by software. Therefore,

a voltage level of this pin is undefined and the power source current may increase while this pin

functions as an input port.

6: This is applied when an external clock is input to pin XIN.

7: Set pin P42/

φ1 as pin P42. (Clock φ1 output is disabled.) And then, for this pin, do the same

handling as that for pins P43 to P47, P5 to P8 and P10.

8: When leaving port P9 pins open after writing data to the port P9 register, note the following: these

pins are in a floating state from reset until the data is written to the port P9 register by software.

Therefore, voltage levels of these pins are undefined and the power source current may increase

while they are in a floating state.

P42–P47, P5–P8, P10

AVSS

VREF

HOLD

RDY

Left open

VCC

VSS

AVCC

XOUT

EVL0

EVL1



When setting ports to input mode

BHE

ALE

HLDA

Left open

P42–P47, P5–P10

AVSS

VREF

HOLD

RDY

Left open

VSS

AVCC

XOUT

EVL0

EVL1



When setting ports to output mode

BHE

ALE

HLDA

Left open

VCC

1.3 Pin description

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