7733 datasheet(828/940 Pages) RENESAS

828 / 940 page

7736 Group User’s Manual

3–6

PROGRAMMABLE I/O PORTS

3.2 Port peripheral circuits

Figures 3.2.1 and 3.2.2 show the port peripheral circuits.

3.2 Port peripheral circuits

Fig. 3.2.1 Port peripheral circuits (1)

•Ports P62/INT0 to P64/INT2 (Inside dotted-line included)

Ports P104/KI0 to P107/KI3 (Inside dotted-line not included)

Port direction register

Port latch

Data bus

Pull-up selection

Pull-up

transistor

Ports P50/TA0OUT, P52/TA1OUT, P54/TA2OUT, P56/TA3OUT, P60/TA4OUT, P82/RxD0/CLKS0

(Inside dotted-line included, and shaded area not included)

•Ports P83/TxD0, P87/TxD1 (Inside dotted-line not included, and shaded area included)

Note 1: Valid only when used as pin

TxDj for serial I/O.

Port direction register

Port latch

Data bus

Output

“1”

N-channel open-drain

selection (Note 1)

Ports P42/

(Inside dotted-line not included, and shaded area not included)

• Ports P00 to P07, P10 to P17, P20 to P27, P30 to P33, P43 to P46, P100 to P103 (Inside dotted-line not included)

Ports P40/HOLD, P41/RDY, P47, P51/TA0IN, P53/TA1IN, P55/TA2IN, P57/TA3IN, P61/TA4IN, P65/TB0IN to P67/TB2IN/

SUB

, P86/RxD1

(Inside dotted-line included)

Port directionregister

Port latch

Data bus

7733 Datasheet(PDF) 828 Page - Renesas Technology Corp