7733 datasheet(850/940 Pages) RENESAS

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SERIAL I/O

7736 Group User’s Manual

8–4

8.3 Clock synchronous serial I/O mode

Concerning section “8.3 Clock synchronous serial I/O mode,” the 7736 Group differs from the 7733 Group

in the following:

• Table 8.3.2

The other description is the same as that of the 7733 Group. Therefore, refer to part 1:

• “8.3 Clock synchronous serial I/O mode” (page 8-21 in part 1)

Table 8.3.2 Functions of I/O pins in clock synchronous serial I/O mode

Functions

Serial data output

Serial data input

Transfer clock output

Transfer clock input

____

CTS

input

____

RTS

output

Programmable I/O port

____

CTS

input

Programmable I/O port

Method of selection

(They output dummy data when only reception is performed.)

Port P8 direction register’s corresponding bits =“0”

(It can be used as an input port when only transmission is

performed.)

(It can be used as an output port when only transmission is

performed.)

Internal/External clock selection bit = “0”

Internal/External clock selection bit = “1”

____ ____

CTS

/RTS enable bit = “0”

____ ____

CTS

/RTS function selection bit = “0”

____ ____

CTS

/RTS enable bit = “0”

____ ____

CTS

/RTS function selection bit = “1”

____ ____

CTS

/RTS enable bit = “1”

____

CTS

enable bit = “0”

____

CTS

enable bit = “1”

Port P8 direction register: Address 1416

Internal/External clock selection bit: Bit 3 at addresses 3016, 3816, and 6416

____ ____

CTS

/RTS enable bit: Bit 4 at addresses 3416 and 3C16

____ ____

CTS

/RTS function selection bit: Bit 2 at addresses 3416 and 3C16

____

CTS

enable bit: Bit 2 at address 6816

g Pin TxDi outputs “H” level from when a UARTi’s operating mode is selected until transfer starts.

(Pin TxDi is in a floating state when N-channel open-drain output is selected.)

g In UART0, multiple transfer clock output pins can be used. (Refer to Table 8.3.3 in part 1.)

____

Notes 1: The RTS output function is not assigned for UART2.

2: As for CLKS0 and CLKS1, refer to section “8.3.1 (4) Number of transfer clock output pins

(UART0)” in part 1.

Pin name

TxDi

(P83, P87, P93)

RxD0 (P82),

RxD1 (P86)

RxD2 (P92)

CLKi

(P81, P85, P91)

CTS0

/RTS0 (P80),

CTS1

/RTS1 (P84)

(Note 1)

CTS2

(P90)

8.3 Clock synchronous serial I/O mode

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