7733 datasheet(858/940 Pages) RENESAS

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WATCHDOG TIMER

7736 Group User’s Manual

10-2

10.2 Operation description

Concerning chapter “10. WATCHDOG TIMER,” the 7736 Group differs from the 7733 Group in the following

section. Therefore, only the differences are described in this chapter:

• “10.2 Operation description”

The following sections of the 7736 Group are the same as those of the 7733 Group. Therefore, for these

sections, refer to part 1:

• “10.1 Block description” (page 10-2 in part 1)

• “10.3 Precautions for watchdog timer” (page 10-10 in part 1)

10.2 Operation description

Concerning section “10.2 Operation description,” the 7736 Group differs from the 7733 Group in the following:

• Figure 10.2.2

The other description is the same as that of the 7733 Group. Therefore, refer to part 1:

• “10.2 Operation description” (page 10-5 in part 1)

Bit

Bit name

Functions

At reset

Main clock division selection bit

Sub clock external input selection bit

Must be fixed to “0” (Note 2).

Clock prescaler reset bit

Undefined

Oscillation circuit control register 1 (address 6F16)

0: Sub-clock oscillation circuit is operating by

itself. Pin P76 functions as pin XCOUT.

Watchdog timer is used when terminating

stop mode.

1: Sub clock is input from the external.

Pin P76 functions as a programmable

I/O port. Watchdog timer is not used when

terminating stop mode.

—

Not implemented.

Notes 1: When writing to this register, follow the procedure shown in Figure 10.2.3 in part 1.

By writing “1” to this bit, clock prescaler is

initialized.

Undefined

Main clock external input selection bit

0: Main clock is divided by 2.

1: Main clock is not divided by 2.

0: Main-clock oscillation circuit is operating by

itself. Watchdog timer is used when terminating

stop mode.

1: Main clock is input from the external.

Watchdog timer is not used when

terminating stop mode.

This bit is ignored.

2: The case where data “010101012” is written with the procedure shown in Figure 10.2.3

in part 1 is not included.

represents that bits 3 to 7 are not used for the watchdog timer.

(Note 1)

Fig. 10.2.2 Structure of oscillation circuit control register 1

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