7733 datasheet(860/940 Pages) RENESAS

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STOP AND WAIT MODES

7736 Group User’s Manual

11–2

11.2 Clock generating circuit

Concerning chapter “11. STOP AND WAIT MODES” of the 7736 Group, description differs depending on the

external bus mode.

In external bus mode A, refer to the corresponding sections in part 1; in external bus mode B, refer to the

corresponding sections in part 2. Note that, for the structure of the oscillation circuit control register 1, refer

to Figure 11.2.3 in part 3.

• “11.1 Overview”

External bus modes A and B (page 11-2 in part 1)

• “11.2 Clock generating circuit”

External bus mode A (page 11-3 in part 1)

External bus mode B (page 11-2 in part 2)

• “11.3 Stop mode”

External bus mode A (page 11-6 in part 1)

External bus mode B (page 11-3 in part 2)

• “11.4 Wait mode”

External bus mode A (page 11-13 in part 1)

External bus mode B (page 11-6 in part 2)

Bit

Bit name

Functions

At reset

Main clock division selection bit

Sub clock external input selection bit

Must be fixed to “0” (Note 2).

Clock prescaler reset bit

Undefined

Oscillation circuit control register 1 (address 6F16)

0: Sub-clock oscillation circuit is operating by

itself. Pin P76 functions as pin XCOUT.

Watchdog timer is used when terminating

stop mode.

1: Sub clock is input from the external.

Pin P76 functions as a programmable

I/O port. Watchdog timer is not used when

terminating stop mode.

—

Not implemented.

Notes 1: When writing to this register, follow the procedure shown in Figure 11.2.4 in part 1.

By writing “1” to this bit, clock prescaler is

initialized.

Undefined

Main clock external input selection bit

0: Main clock is divided by 2.

1: Main clock is not divided by 2.

0: Main-clock oscillation circuit is operating by

itself. Watchdog timer is used when terminating

stop mode.

1: Main clock is input from the external.

Watchdog timer is not used when

terminating stop mode.

This bit is ignored.

2: The case where data “010101012” is written with the procedure shown in Figure 11.2.4

in part 1 is not included.

represents that bits 3 to 7 are not used for the stop and wait modes.

(Note 1)

Fig. 11.2.3 Structure of oscillation circuit control register 1

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