7733 datasheet(107/940 Pages) RENESAS

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KEY INPUT INTERRUPT FUNCTION

7733 Group User’s Manual

5–4

Bit

Functions

Port function control register (address 6D 16)

Bit name

0: Pins P0 to P3 are used for the external bus output.

1: Pins P0 to P3 are used for the port output.

Standby state selection bit

Sub-clock output selection bit/

Timer B2 clock source selection

bit

0: No internal connection

1: Internal connection with timer B2

Timer B1 internal connect

selection bit

Port P6 pull-up selection bit 0

0: No pull-up for pins P54/TA2OUT/KI0 to P57/TA3IN/KI3

1: With pull-up for pins P54/TA2OUT/KI0 to P57/TA3IN/KI3

Port P5 pull-up selection bit

Key input interrupt selection bit

0: INT2 interrupt

1: Key input interrupt

Port P6 pull-up selection bit 1

Must be fixed to “0.”

At reset

•Port-XC selection bitV = “0”

(when the sub clock is not used)

Timer B2 (event counter mode)

clock source selection (Note 1)

0: TB2IN input (event counter mode)

1: Main clock divided by 32

(clock timer)

•Port-XC selection bit = “1”

(when the sub clock is used)

Sub-clock output selection

0: Pin P67/TB2IN/

f SUBfunctions as a

programmable I/O port.

1: Sub clock

f SUBis output from

pin P67/TB2IN/

f SUB.

(Note 2)

Notes 1: When the port-Xc selection bit = “0” and timer B2 operates in the timer mode or the pulse period

/pulse width measurement mode, bit 1 is invalid.

2: When timer B1 operates in the event counter mode, bit 2 is valid.

represents that bits 0 to 4 are not used for the key input interrupt function.

•Key input interrupt selection bit = “0”

0: No pull-up for pin P6 4/INT2

1: With pull-up for pin P6 4/INT2

•Key input interrupt selection bit = “1”

0: Pin P64/INT2 is a port with no pull-up.

1: Pin P64/INT2 is an input pin with pull-up

and is used for the key input interrupt.

0: No pull-up for pins P62/INT0 and P63/INT1

1: With pull-up for pins P62/INT0 and P63/INT1

Port-Xc selection bitV : Bit 4 of the oscillation circuit control register 0 (address 6C 16)

5.2.2 Port function control register

Figure 5.2.3 shows the structure of the port function control register.

5.2 Block description

Fig. 5.2.3 Structure of port function control register

7733 Datasheet(PDF) 107 Page - Renesas Technology Corp

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