7733 datasheet(114/940 Pages) RENESAS

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TimerA1

TIMER A

7733 Group User’s Manual

6–3

6.2 Block description

Figure 6.2.1 shows the timer A block diagram. Registers related to timer A are described below.

Fig. 6.2.1 Timer A block diagram

6.2 Block description

Data bus (Odd)

Data bus (Even)

f 2

f 16

f 64

f 512

Clock source

selection

•Timer mode

•One-shot pulse mode

•PWM mode

Polarity

switching

Timer mode

(Gate function)

Event counter mode

External trigger

Count start flag

Countdown

Up-down flag

(Low-order 8 bits)

(High-order 8 bits)

Timer Ai reload register (16)

Timer Ai counter (16)

Timer Ai

interrupt

request bit

Countup/Countdown

switching

“Countdown” is selected

when not in the event

counter mode.

Toggle

F.F.

Pulse output function

selection bit

TAiIN

(i = 0 to 4)

TAiOUT

(i = 0 to 4)

Clocks f2, f16, f64, and f512:Refer to chapter “14. CLOCK GENERATING CIRCUIT.”

(address 4016 )

(address 4416 )

TimerA0

4716 4616

4916 4816

TimerA2

4B16 4A16

TimerA3

4D16 4C16

TimerA4

4F16 4E16

addresses

7733 Datasheet(PDF) 114 Page - Renesas Technology Corp

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