7733 datasheet(181/940 Pages) RENESAS

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TIMER B

7733 Group User’s Manual

7–18

7.4 Event counter mode

Fig. 7.4.1 Structures of timer Bi mode register and timer Bi register in event counter mode

0 0: Counting is performed at the falling

edge of the external signal.

0 1: Counting is performed at the rising

edge of the external signal.

1 0: Counting is performed at both

falling and rising edges of the

external signal.

1 1: Do not select.

Timer Bi mode register (i = 0 to 2) (addresses 5B16 to 5D16)

Bit

This bit is ignored in the event counter mode and is undefined at reading.

•Timer B0 mode register

Must be fixed to “0.”

Count polarity selection bits

Operating mode selection bits

Bit name

Functions

0 1: Event counter mode

b1 b0

b3 b2

These bits are ignored in the event counter mode.

At reset

Un-

defined

Un-

defined

•Timer B1 and B2 mode registers

Not implemented.

(b15)

(b8)

Timer B0 register (addresses 5116, 5016)

Timer B1 register (addresses 5316, 5216)

Timer B2 register (addresses 5516, 5416)

Functions

Bit

At reset

15 to 0 Values 000016 to FFFF16 can be set.

Assuming that the set value = n, counter

divides the count source frequency by (n + 1).

At reading this register, the counter value is

read out.

Un-

defined

—

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