7733 datasheet(235/940 Pages) RENESAS

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SERIAL I/O

7733 Group User’s Manual

8–32

8.3.4 Transmit operation

When the transmit conditions described in section “8.3.3 Method of transmission” are satisfied while an

internal clock is selected, the transfer clock is generated. And then, the following operations are automatically

performed after one cycle of the transfer clock has passed.

When the transmit conditions are satisfied and the external clock is input to the CLKi pin while the external

clock is selected, the following operations are automatically performed.

q The UARTi transmission buffer register’s contents is transferred to the UARTi transmission register.

q The transmission buffer empty flag is set to “1.”

q The transmission register empty flag is cleared to “0.”

q A UARTi transmission interrupt request occurs and the interrupt request bit is set to “1.”

q Eight transfer clocks are generated (when an internal clock is selected).

The transmit operation is described below.

Data in the UARTi transmission register is transmitted from the TxDi pin synchronously with the valid

edgeg of the CLKi pin’s clock.

This data is transmitted bit by bit sequentially beginning with the least significant bit (LSB).

When one byte of data has been transmitted, the transmission register empty flag is set to “1.” This

indicates the completion of transmission.

Valid edgeg: In UART0 and UART1, this means the falling edge when the CLK polarity selection bit = “0”

and the rising edge when the CLK polarity selection bit = “1”; in UART2, this means the

rising edge.

Figure 8.3.7 shows the transmit operation.

When an internal clock is selected, if the transmit conditions for the next data are satisfied at completion

of transmission, the next transfer clock is generated immediately. Accordingly, when performing transmission

in succession, set the next transmit data to the UARTi transmission buffer register during transmission

(when the transmission register empty flag = “0”). When the transmit conditions for the next data are not

satisfied, the transfer clock stops at “H” level when the CLK polarity selection bit = “0,” and it stops at “L”

level when the CLK polarity selection bit = “1.”

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Figure 8.3.8 shows an example of transmit timing (when an internal clock and the CTS function are

selected).

8.3 Clock synchronous serial I/O mode

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