7733 datasheet(238/940 Pages) RENESAS

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SERIAL I/O

7733 Group User’s Manual

8–35

8.3 Clock synchronous serial I/O mode

8.3.5 Method of reception

Figures 8.3.10 and 8.3.11 show initial setting examples for related registers when receiving. Reception is

started when all of the following conditions ( to ) are satisfied. When an external clock is selected,

satisfy conditions to with the following preconditions satisfied.

[Preconditions for UART0 and UART1]

• The CLKi pin’s input is at “H” level.

(When an external clock is selected and the CLK polarity selection bit = “0.”)

• The CLKi pin’s input is at “L” level.

(When an external clock is selected and the CLK polarity selection bit = “1.”)

Note: When an internal clock is selected, the above preconditions are ignored.

[Preconditions for UART2]

• The CLKi pin’s input is at “H” level.

(When an external clock is selected)

Note: When an internal clock is selected, the above precondition is ignored.

Receive enable state (receive enable bit = “1”)

Transmit enable state (transmit enable bit = “1”)

Dummy data is present in the UARTi transmission buffer register (transmission buffer empty flag = “0”).

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By connecting the RTSi pin (receiver side) and CTSi pin (transmitter side), the timing of transmission and

that of reception can be matched (UART0, UART1). For details, refer to section “8.3.6 Receive operation.”

When using interrupts, settings for enabling interrupts are required. For details, refer to chapter “4.

Interrupts.”

Figure 8.3.12 shows the processing after reception is completed.

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