7733 datasheet(242/940 Pages) RENESAS

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SERIAL I/O

7733 Group User’s Manual

8–39

8.3 Clock synchronous serial I/O mode

8.3.6 Receive operation

When the receive conditions described in section “8.3.5 Method of reception” are satisfied while an

internal clock is selected, the transfer clock is generated. And then, the receive is started after one cycle

of the transfer clock has passed.

When the receive conditions are satisfied while the external clock is selected, UARTi is in the reception

enabled state. Then, the external clock is input to the CLKi pin and reception is started.

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In UART0 and UART1, when the RTS function is selected with an external clock selected, the RTSi pin’s

output level is “L,” and the microcomputer informs the transmitter side that reception is enabled. When

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reception is started, the RTSi pin’s output level is “H.” Accordingly, by connecting the RTSi pin to the CTSi

pin of the transmitter side, the timing of transmission and that of reception can be matched.

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When an internal clock is selected, do not use the RTS function because the RTSi output is undefined.

Figure 8.3.13 shows a connection example.

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The RTS output function is not assigned for UART2.

The receive operation is described below.

The signal which is input from the RxDi pin is taken in the most significant bit of the UARTi receive

the CLKi pin.

The contents of the UARTi receive register is shifted by 1 bit to the right.

Operations and are repeated at each valid edge of the clock which is output from the CLKi pin or

input to the CLKi pin.

When one byte of data is prepared in the UARTi receive register, the contents of this register is

transferred to the UARTi receive buffer register.

Simultaneously with , the receive completion flag is set to “1.” At this time, a receive interrupt request

occurs, and then an interrupt request bit is set to “1.”

Valid edgeg : In UART0 and UART1, this means the rising edge when the CLK polarity selection bit = “0”

and the falling edge when the CLK polarity selection bit = “1”; in UART2, this means the rising

edge.

The receive completion flag is cleared to “0” when the low-order byte of the UARTi receive buffer register

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is read out. The RTSi pin continues to output “H” level until the receive conditions are next satisfied (when

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the RTS function is selected). Figure 8.3.14 shows the receive operation and Figure 8.3.15 shows an

example of receive timing (when an external clock is selected).

When the contents of the UARTi receive buffer register is read out with the transfer format selection bit

= “1” (MSB first), each bit’s position of this register’s contents is reversed and the resultant data is read

out (UART0, UART1).

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