7733 datasheet(244/940 Pages) RENESAS

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SERIAL I/O

7733 Group User’s Manual

8–41

8.3 Clock synchronous serial I/O mode

1 / fEXT

(Note) RTSi

CLKi

RxDi

“H”

“L”

“0”

“1”

“0”

“1”

“0”

“1”

“0”

“1”

“0”

“1”

D0 D1 D2 D3 D4 D5 D6 D7

D1 D2

D3 D4

Dummy data is set in UARTi transmission buffer register.

Transmit enable bit

Transmission buffer

empty flag

Receive completion flag

Receive enable bit

Received data is taken in.

UARTi transmission register

← UARTi transmission buffer register

UARTi receive buffer register is read out.

The above timing diagram is applied when

the following conditions are satisfied:

External clock is selected.

RTS

function is selected.

CLK polarity selection bit = “0.”

fEXT: Frequency of external clock

When the CLKi pin’s input level is “H,” satisfy the

following conditions:

Transmit enable bit

→ “1”

Receive enable bit

→ “1”

Writing of dummy data to UARTi transmission

buffer register

UARTi receive register

→ UARTi receive buffer register

UARTi receive

interrupt request bit

Cleared to “0” when an interrupt request is accepted; otherwise,

cleared by software.

Note: The RTSi output function is not assigned for UART2.

Fig. 8.3.15 Example of receive timing (when external clock is selected)

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