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7733 Datasheet(PDF) 251 Page - Renesas Technology Corp |
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7733 Datasheet(HTML) 251 Page - Renesas Technology Corp |
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251 / 940 page ![]() SERIAL I/O 7733 Group User’s Manual 8–48 8.4 Clock asynchronous serial I/O (UART) mode DATA (8 bits) Time Next transmit/receive data (When transferring in succession) For the case where 1ST-8DATA-1PAR-1SP “H” ST LSB MSB PAR SP ST Transmit/Receive data Fig. 8.4.2 Example of transfer data format Table 8.4.6 Each bit in transmit data Name ST Start bit DATA Character bit PAR Parity bit SP Stop bit Functions “L” signal equivalent to 1 character bit which is added immediately before the character bits. It indicates start of data transmission. Transmit data which is set in the UARTi transmission buffer register. A signal which is added immediately after the character bits in order to improve data reliability. The level of this signal changes depending on odd/even parity selection in such a way that the sum of “1”s in bits (this bit and character bits) is always an odd or even number. “H” level signal equivalent to 1 or 2 character bits which is added immediately after the character bits (or parity bit when parity is enabled). It indicates end of data transmission. |
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