7733 datasheet(253/940 Pages) RENESAS

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SERIAL I/O

7733 Group User’s Manual

8–50

8.4 Clock asynchronous serial I/O (UART) mode

UART0 baud rate register (BRG0) (address 3116)

UART1 baud rate register (BRG1) (address 3916)

UART2 baud rate register (BRG2) (address 6516)

A value from 0016 to FF16 is set.

Interrupt priority level selection bits

When using interrupts, one of level 1

to 7 must be set.

When disabling interrupts, level 0 must

be set.

Note 2: The CTS/RTS function selection

bit is valid when the CTS/RTS

enable bit = “0.”

UART0 transmission interrupt control register (address 7116)

UART1 transmission interrupt control register (address 7316)

A-D/UART2 transm./rece. interrupt control register (address 7016)

UART0 transmit/receive control register 1 (address 3516)

UART1 transmit/receive control register 1 (address 3D16)

UART2 transmit/receive control register 1 (address 6916)

Transmit enable bit

1: Transmission is enabled.

Transmission is started.

(If the CTS function is selected, transmission is

started when the CTSi pin’s input level is “L.”)

UART0 transmission buffer register (addresses 3316, 3216)

UART1 transmission buffer register (addresses 3B16, 3A16)

UART2 transmission buffer register (addresses 6716, 6616)

Transmit data is set here.

UART0 transmit/receive mode register (address 3016)

UART1 transmit/receive mode register (address 3816)

UART2 transmit/receive mode register (address 6416)

Internal/External clock selection bit

0: Internal clock

1: External clock

1 0 0: UART mode (7 bits)

1 0 1: UART mode (8 bits)

1 1 0: UART mode (9 bits)

Stop bit length selection bit

0: 1 stop bit

1: 2 stop bits

Odd/Even parity selection bit

0: Odd parity

1: Even parity

Parity enable bit

0: Parity is disabled.

1: Parity is enabled.

Sleep selection bit (Note 1)

0: The sleep mode is terminated (ignored).

1: The sleep mode is selected.

b2b1b0

UART0 transmit/receive control register 0 (address 3416)

UART1 transmit/receive control register 0 (address 3C16)

BRG count source selection bits

CTS

/ RTS enable bit

0: The CTS / RTS function is enabled.

1: The CTS / RTS function is disabled.

CTS

/ RTS function selection bit

0: The CTS function is selected.

1: The RTS function is selected.

(The CTS function is disabled.)

Data output selection bit

0: TxDi pin is set for CMOS output.

1: TxDi pin is set for N-channel

open-drain output.

Clocks f2, f16, f64, and f512 : Refer to chapter “14. CLOCK GENERATING

CIRCUIT.”

0 0: Clock f2

0 1: Clock f16

1 0: Clock f64

1 1: Clock f512

b1b0

(Note 2)

Note 1: Nothing is allocated to bit

7 of the UART2 transmit/

receive mode register.

BRG count source selection bits

CTS

enable bit

0: The CTS function is enabled.

1: The CTS function is disabled (I/O port).

0 0: Clock f2

0 1: Clock f16

1 0: Clock f64

1 1: Clock f512

b1b0

UART2 transmit/receive control register 0 (address 6816)

Fig. 8.4.3 Initial setting example for related registers when transmitting

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