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7733 Datasheet(PDF) 257 Page - Renesas Technology Corp |
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7733 Datasheet(HTML) 257 Page - Renesas Technology Corp |
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257 / 940 page  7733 Group User’s Manual 8–54 8.4 Clock asynchronous serial I/O (UART) mode Fig. 8.4.7 Example of transmit timing when data is transferred in 9 bits (When parity is disabled and two stop bits) Fig. 8.4.6 Example of transmit timing when data is transferred in 8 bits (When parity is enabled, one ____ stop bit, and CTS function is not selected) ST D0 TENDi TxDi D0 D1 D2 D3 D4 D5 D6 D7 ST D8 D0 D1 D2 D3 D4 D5 D6 D7 ST SP D1 D8 SP SP SP “0” “1” “0” “1” “0” “1” Tc “0” “1” Transmit enable bit Transmission buffer empty flag Transmission register empty flag Start bit Data is set in UARTi transmission buffer register. Transfer clock TENDi : Next transmit conditions are checked when this signal level becomes “H.” (TENDi is an internal signal. Accordingly, it cannot be read from the external.) The above timing diagram is applied when the following conditions are satisfied: q Parity is disabled. q 2 stop bits q CTS function is not selected. TC = 16(n + 1)/fi or 16(n + 1)/fEXT fi : BRGi’s count source frequency (f2, f16, f64, or f512) fEXT : BRGi’s count source frequency (external clock) n : Value set to BRGi Stopped because transmit enable bit = “0” UARTi transmission interrupt request bit Cleared to “0” when an interrupt request is accepted; otherwise, cleared by software. Stop bit Stop bit UARTi transmission register UARTi transmission buffer register Tc D0 D1 D2 D3 D4 D5 D6 D7 ST P SP D0 D1 D0 D1 D2 D3 D4 D5 D6 D7 ST P SP ST TENDi TxDi “0” “1” “0” “1” “0” “1” “0” “1” Transmit enable bit Transmission buffer empty flag Transmission register empty flag Start bit Stop bit Data is set in UARTi transmission buffer register. Transfer clock The above timing diagram is applied when the following conditions are satisfied: q Parity is enabled. q 1 stop bit q CTS function is not selected. TC = 16(n + 1)/fi or 16(n + 1)/fEXT fi : BRGi’s count source frequency (f2, f16, f64, or f512) fEXT : BRGi’s count source frequency (external clock) n : Value set to BRGi Stopped because transmit enable bit = “0” UARTi transmission interrupt request bit Cleared to “0” when an interrupt request is accepted; otherwise, cleared by software. Parity bit TENDi : Next transmit conditions are checked when this signal level becomes “H.” (TENDi is an internal signal. Accordingly, it cannot be read from the external.) UARTi transmission register UARTi transmission buffer register SEIRAL I/O |
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