7733 datasheet(260/940 Pages) RENESAS

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SERIAL

I/O

7733 Group User’s Manual

8–57

8.4 Clock asynchronous serial I/O (UART) mode

Then, reception starts when the start

bit is detected.

Port P8 direction register (address 14 16)

RxD0 pin

RxD1 pin

UART0 baud rate register (BRG0) (address 31 16)

UART1 baud rate register (BRG1) (address 39 16)

UART2 baud rate register (BRG2) (address 65 16)

A value from 0016 to FF16 is set.

UART0 receive interrupt control register (address 72 16)

UART1 receive interrupt control register (address 74 16)

A-D/UART2 trans./rece. interrupt control register (address 70 16)

Interrupt priority level selection bits

When using interrupts, one of level 1 to

7 must be set.

When disabling interrupts, level 0 must

be set.

Note 2: The CTS/RTS function selection

bit is valid when CTS/RTS enable

bit = “0.”

g Set the transfer data format in the

same way as set on the transmitter side.

Note 1: Nothing is allocated to bit 7 of UART2

transmit/receive mode register.

UART0 transmit/receive control register 1 (address 35 16)

UART1 transmit/receive control register 1 (address 3D 16)

UART2 transmit/receive control register 1 (address 69 16)

Receive enable bit

1: Reception is enabled.

UART0 transmit/receive mode register (address 30 16)

UART1 transmit/receive mode register (address 38 16)

UART2 transmit/receive mode register (address 64 16)

Internal/External clock selection

bit

0: Internal clock

1: External clock

1 0 0: UART mode (7 bits)

1 0 1: UART mode (8 bits)

1 1 0: UART mode (9 bits)

Stop bit length selection bit

0: 1 stop bit

1: 2 stop bits

Odd/Even parity selection bit

0: Odd parity

1: Even parity

Parity enable bit

0: Parity is disabled.

1: Parity is enabled.

Sleep selection bit (Note 1)

0: The sleep mode is terminated (ignored) .

1: The sleep mode is selected.

b2b1b0

UART0 transmit/receive control register 0 (address 34 16)

UART1 transmit/receive control register 0 (address 3C 16)

BRG count source selection bits

CTS

/ RTS enable bit

0: The CTS / RTS function is enabled.

1: The CTS / RTS function is disabled.

CTS

/RTS function selection bit (Note 2)

0: The CTS function is selected.

(The RTS function is disabled.)

1: The RTS function is selected.

Clocks f2, f16, f64, and f512: Refer to chapter “14. CLOCK GENERATING

CIRCUIT.”

0 0: Clock f2

0 1: Clock f16

1 0: Clock f64

1 1: Clock f512

b1b0

BRG count source selection bits

CTS

enable bit

0: The CTS function is enabled.

1: The CTS function is disabled (I/O port).

0 0: Clock f2

0 1: Clock f16

1 0: Clock f64

1 1: Clock f512

b1b0

Port P7 direction register (address 11 16)

RxD2 pin (Note 3)

Note 3: In the 7733 Group or the 7735

Group, set this bit.

In the 7736 Group, it is not

neccessary to set this bit.

UART2 transmit/receive control register 0 (address 68 16)

Fig. 8.4.9 Initial setting example for related registers when receiving

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