7733 datasheet(262/940 Pages) RENESAS

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SERIAL I/O

7733 Group User’s Manual

8–59

8.4 Clock asynchronous serial I/O (UART) mode

TxDi

RxDi

CTSi

TxDi

RxDi

RTSi (Note)

Transmitter side

Receiver side

Note: The RTSi output function is not assigned for

8.4.6 Receive operation

When the receive enable bit is set to “1,” the UARTi enters the receive enable state. And then, the transfer

clock is generated when ST is detected, and reception is started.

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When the RTS function is selected (UART0, UART1), the RTSi pin’s output level becomes “L” if the UARTi

enters the receive enable state and the microcomputer informs the transmitter side that reception is

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enabled. When reception is started, the RTSi pin’s output level becomes “H.” Accordingly, by connecting

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the RTSi pin (receiver side) and the CTSi pin (transmitter side), the timing of transmission and that of

reception can be matched. Figure 8.4.11 shows an connection example.

The receive operation is described below.

The signal which is input from the RxDi pin is taken in the most significant bit of the UARTi receive

The contents of UARTi receive register is shifted by 1 bit to the right.

Operations and are repeated at each transfer clock’s rising edge.

When a set of data is prepared, in other words, when shifted several times depending on the specified

data format, the UARTi receive register’s contents is transferred to the UARTi receive buffer register.

Simultaneously with , the receive completion flag is set to “1.” Furthermore, a UARTi receive interrupt

request occurs and the interrupt request bit is set to “1.”

The receive completion flag is cleared to “0” when the low-order of the UARTi receive buffer register is read

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out. The RTSi pin’s output level becomes “L” simultaneously with (when RTS function is selected). Figure

8.4.12 shows an example of receive timing when transfer data has a length of 8 bits.

Fig. 8.4.11 Connection example

7733 Datasheet(PDF) 262 Page - Renesas Technology Corp