7733 datasheet(264/940 Pages) RENESAS

264 / 940 page

SERIAL

I/O

7733 Group User’s Manual

8–61

8.4 Clock asynchronous serial I/O (UART) mode

8.4.7 Processing when error is detected

Errors listed below can be detected in the UART mode:

q Overrun error

An overrun error occurs when the next data is prepared in the UARTi receive register with the receive

completion flag = “1” (in other words, data is present in the UARTi receive buffer register), and then

the next data is transferred to the UARTi receive buffer register. In other words, when the next data

is prepared before the contents of the UARTi receive buffer register is read out. When an overrun error

occurs, the next receive data is written into the UARTi receive buffer register. At this time, the UARTi

receive interrupt request bit is not set to “1.”

q Framing error

A framing error occurs when the number of detected stop bits does not match the number which is

set. (The UARTi interrupt request bit is set to “1.”)

q Parity error

A parity error occurs when the sum of “1”s in the parity bit and character bits does not match the

number which is set. (The UARTi interrupt request bit is set to “1.”)

Each error is detected when data is transferred from the UARTi receive register to the UARTi receive buffer

the error sum flag is set to “1.” Accordingly, the error sum flag informs whether any error has occurred or

not.

Error flags are cleared to “0” when the serial I/O mode selection bits are cleared to “0002” or when the

receive enable bit is cleared to “0.” (When all of the overrun, framing, and parity error flags are cleared

to “0,” the error sum flag is cleared to “0.”) Note also that the framing and parity error flags are cleared

to “0” when the low-order byte of the UARTi receive buffer register is read out.

When an error occurs during reception, initialize the error flags and the UARTi receive buffer register, and

then perform reception again. When it is necessary to perform transmission again owing to an error which

occurs in the receiver side, set the UARTi transmission buffer register again, and then starts transmission

again.

The method of initializing the UARTi receive buffer register and that of setting the UARTi transmission

buffer register again are described below.

(1) Method of initializing UARTi receive buffer register

Clear the receive enable bit to “0.” (Reception is disabled.)

Set the receive enable bit to “1” again. (Reception is enabled.)

(2) Method of setting UARTi transmission buffer register again

Clear the serial I/O mode selection bits to “0002.” (Serial I/O is ignored.)

Set the serial I/O mode selection bits again.

Set the transmit enable bit to “1.” (Transmission is enabled.) And set the transmit data to the UARTi

transmission buffer register.

8.4.8 Precautions for UART

For performing the transmission and the reception simultaneously, UART2 does not distinguish the transmission

interrupt from the reception interrupt. The UART2 transmission/reception interrupt request occurs when

either interrupt request occurs. Accordingly, in the system which performs the transmission and reception

simultaneously for UART2, not use the UART2 transmission/reception interrupt but use the method of

poling the transmission buffer empty flag and the receive completion flag by software.

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