7733 datasheet(321/940 Pages) RENESAS

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STOP AND WAIT MODES

7733 Group User’s Manual

11–14

11.4 Wait mode

Table 11.4.2 Pin state in wait mode

State

Single-chip mode

Memory expansion

Microprocessor mode

mode

Pins

When the standby state

selection bit∗1 = “0”

When the standby state

selection bit∗1 = “1”

s When the signal output

disable selection bit =

“0,” “H” level is output.

s When the signal output

disable selection bit =

“1,” “L” level is output.

s When the signal output

disable selection bit =

“0,” “H” level is output.

s When the signal output

disable selection bit =

“1,” “L” level is output.

Same as in the micro-

processor mode

“H” level is output.

R/W,

____

BHE,

_____

HLDA

ALE

A0–A7,

A8/D8–A15/D15,

A16/D0–A23/D7

Output levels can be set.

(Refer to section

“11.4.2 Output levels

of external bus and

bus control signals

in wait mode”)

“L” level is output.

s When the signal output

disable selection bit*3 = “0”

φ1: Operating when the

system clock stop bit at

wait state = “0.”

“L” level is output when

the system clock stop

bit at wait state = “1.”

s When the signal output

disable selection bit = “1”

P42: Bit 2’s value of port P4

s When the clock

φ1 output selection bit*2 = “1”

φ1: Operating when the system clock stop bit

at wait state*4 = “0.”

“L” level is output when the system clock

stop bit at wait state = “1.”

s When the clock

φ1 output selection bit = “0”

P42: Retains the same state

in which the WIT instruction is

executed.

P42/

φ1

Retains the same

state in which the

WIT instruction is ex-

ecuted.

P43 to P47, P5 to P8

: Retains the same state

in which the WIT instruction is executed.

Ports

P0 to P8

(not including P42)

: Retains the same

state in which

the WIT instruction

is executed.

Standby state selection bit*1: Bit 0 at address 6D16 (Refer to Figure 11.4.1.)

Clock

φ1 output selection bit*2: Bit 7 at address 5E16

(Refer to section “12.1 Signals required for accessing external devices.”)

Signal output disable selection bit*3: Bit 6 at address 6C16

(Refer to section “12.1 Signals required for accessing external devices.”)

System clock stop bit at wait state*4: Bit 5 at address 6C16

(Refer to section “11.4.1 State of clocks f2 to f512 in wait mode.”)

Note: Make sure to set bit 2 of the port P4 direction register to “1.”

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