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STOP AND WAIT MODES

7733 Group User’s Manual

11–10

When using the watchdog timer in termination of the stop mode, make sure to set as follows before

executing the STP instruction.

s Enable an interrupt which is used for termination.

Also, make sure that the interrupt priority level of an interrupt which is used for termination is higher

than the processor interrupt priority level (IPL) of a routine where the STP instruction is executed.

Furthermore, when multiple interrupts in Table 11.3.3 are enabled, the stop mode is terminated by the

interrupt request which occurs first.

After oscillation starts (), there is a possibility that an interrupt request occurs until the supply of

internal clock

φ starts (). Interrupt requests which occur during this period are accepted in order of

priority after the watchdog timer’s MSB becomes “0.” For interrupts which have no need to be

accepted, set their interrupt priority levels to “0” (Interrupt disabled) before executing the STP instruction.

s When the system clock is the main clock or the main clock divided by 8, set the main clock external

input selection bit (bit 1 at address 6F16; Refer to Figure 11.2.3.) to “0.” When the system clock is

the sub clock, set the sub clock external input selection bit (bit 2 at address 6F16) to “0.”

11.3.3 Stop mode terminating operation by interrupt request occurrence (when not using watchdog timer)

When a clock is stably input from the external to a clock input pin (Refer to Figures 14.2.2 and 14.2.4.),

instruction execution can be started immediately after the termination of the stop mode.

When an interrupt request occurs, clock input from pin XIN starts. Simultaneously, supply of clocks f2

to f512 starts.

Supply of internal clock

φ starts after 7 cycles of f2.

The interrupt request which occurs in is accepted.

Table 11.3.3 lists interrupts which can be used for termination.

When not using the watchdog timer in termination of the stop mode, make sure to set as follows before

executing the STP instruction.

s Enable an interrupt which is used for termination.

Also, make sure that the interrupt priority level of an interrupt which is used for termination is higher

than the processor interrupt priority level (IPL) of a routine where the STP instruction is executed.

Furthermore, when multiple interrupts in Table 11.3.3 are enabled, the stop mode is terminated by the

interrupt request which occurs first.

s When the system clock is the main clock or the main clock divided by 8, set the main clock external

input selection bit (bit 1 at address 6F16; Refer to Figure 11.2.3.) to “1.” When the system clock is the

sub clock, set the sub clock external input selection bit (bit 2 at address 6F16) to “1.”

11.3 Stop mode

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