7733 datasheet(313/940 Pages) RENESAS

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STOP AND WAIT MODES

7733 Group User’s Manual

11–6

11.3 Stop mode

When the STP instruction is executed, the main-clock and sub-clock oscillation circuits stop operating. This

state is called “stop mode.”

In the stop mode, even when oscillation stops, the contents of the internal RAM can be retained if there

is 2 V of Vcc (power source voltage) or more. Furthermore, because the CPU and all internal peripheral

devices which use clocks f2 to f512*1 stop operating, power consumption is lowered. Refer to section “17.4

Power saving” for lowering the power consumption.

Table 11.3.1 lists the microcomputer’s state/operation in the stop mode and after the stop mode is terminated.

Table 11.3.2 lists the pin state in the stop mode.

Table 11.3.1 Microcomputer’s state/operation in stop mode and after stop mode is terminated

11.3 Stop mode

State in

stop mode

Operation

after stop

mode is

terminated

When terminated by

interrupt request

occurrence

When terminated by

hardware reset

Item

f(XIN)/32

f(XCIN)/32

Stopped

Operating enabled only in the event counter mode

Operating enabled only when the external clock is selected

Stopped

Refer to Table 11.3.2

Clocks f2 to f512*1, clock

φ1*2 : Refer to Figure 11.2.1.

Clock timer*3 : Refer to section “7.6 Clock timer.”

Clock input pin*4 : When the system clock is the main clock, pin XIN is used; when the system clock is the

sub clock, pin XCIN is used.

g In order to select whether to use the watchdog timer or not when terminating the stop mode, specify the main clock

external input selection bit (bit 1 at address 6F16; when the main clock is used) or the sub clock external input

selection bit (bit 2 at address 6F16; when the sub clock is used).

(Refer to Figure 11.2.3, sections “11.3.2 Stop mode terminating operation by interrupt request occur-

rence (when using watchdog timer)” and “11.3.3 Stop mode terminating operation by interrupt

request occurrence (when not using watchdog timer).”

State/Operation

Watchdog timer is used

when terminating the stop mode

Watchdog timer is not used

when terminating the stop mode

Supply of internal clock

φ starts

after measuring a certain time

by watchdog timer.

Operation after hardware reset

Supply of internal clock

starts after f2 x 7 cycles.

Condition

From the external, a clock

must stably be input to a

clock input pin*4.

Oscillation

Internal clock

Clocks f2 to f512*1, clock

φ1*2

Clock

timer*3

Timer A, Timer B

Serial I/O

A-D converter

Watchdog timer

Pins

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