7733 datasheet(314/940 Pages) RENESAS

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STOP AND WAIT MODES

7733 Group User’s Manual

11–7

Table 11.3.2 Pin state in stop mode

11.3 Stop mode

State

Single-chip mode

Memory expansion

Microprocessor mode

mode

Pins

When the standby state

selection bit∗1 = “0”

When the standby state

selection bit∗1 = “1”

s When the signal output

disable selection bit =

“0,” “H” level is output

s When the signal output

disable selection bit =

“1,” “L” level is output.

s When the signal output

disable selection bit =

“0,” “H” level is output.

s When the signal output

disable selection bit =

“1,” “L” level is output.

Same as in the micro-

processor mode

“H” level is output.

R/W,

____

BHE,

_____

HLDA

ALE

A0–A7,

A8/D8–A15/D15,

A16/D0–A23/D7

“L” level is output.

Retains the same

state in which the

STP instruction is

executed.

s When the clock

φ1 output selection

bit*2 = “1”

φ1: “L” level is output.

s When the clock

φ1 output selection

bit = “0”

P42: Retains the same state in which

the STP instruction is executed.

P0 to P8

(not including P42)

: Retains the same

state in which the

STP instruction is

executed.

P43 to P47, P5 to P8

:Retains the same state

in which the STP instruction is executed.

Ports

s When the signal output disable

selection bit*3 = “0”

φ1: “L” level is output.

s When the signal output disable

selection bit = “1”

P42: Bit 2’s value of the port P4

P42/

φ1

Standby state selection bit*1: Bit 0 at address 6D16 (Refer to Figure 11.3.1.)

Clock

φ1 output selection bit*2: Bit 7 at address 5E16

(Refer to section “12.1 Signals required for accessing external devices.”)

Signal output disable selection bit*3: Bit 6 at address 6C16

(Refer to section “12.1 Signals required for accessing external devices.”)

Note: Make sure to set bit 2 of the port P4 direction register to “1.”

11.3.1 Output levels of external bus and bus control signals in stop mode

In the memory expansion or microprocessor mode, the output levels of the external bus and bus control

signals in the stop mode can be set by software. By setting the standby state selection bit (bit 0 at address

6D16) to “1,” these output levels become levels set by software. Figure 11.3.1 shows an output level setting

example in the stop mode.

In the single-chip mode, do not set the standby state selection bit to “1.”

Output levels can be

set. (Refer to section

“11.3.1 Output levels

of external bus and

bus control signals

in stop mode.”)

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