| Electronic Components Datasheet Search |
|
7751 Datasheet(PDF) 63 Page - Renesas Technology Corp |
|
|
|||||||||||||||||||||||||||||
7751 Datasheet(HTML) 63 Page - Renesas Technology Corp |
|
63 / 540 page ![]() 7751 Group User’s Manual INTERRUPTS 4–8 4.3.1 Interrupt disable flag (I) All maskable interrupts can be disabled by this flag. When this flag is set to “1,” all maskable interrupts are disabled; when the flag is cleared to “0,” those interrupts are enabled. Because this flag is set to “1” at reset, clear the flag to “0” when enabling interrupts. 4.3.2 Interrupt request bit When an interrupt request occurs, this bit is set to “1.” The bit remains set to “1” until the interrupt request is accepted, and it is cleared to “0” when the interrupt request is accepted. This bit also can be set to “0” or “1” by software. ____ ____ For the INTi interrupt request bit (i = 0 to 2), when using the INTi interrupt with level sense, the bit is ignored. 4.3.3 Interrupt priority level select bits and processor interrupt priority level (IPL) The interrupt priority level select bits are used to determine the priority level of each interrupt. Use the SEB or CLB instruction to set these bits. When an interrupt request occurs, its interrupt priority level is compared with the processor interrupt priority level (IPL). The requested interrupt is enabled only when the comparison result meets the following condition. Accordingly, an interrupt can be disabled by setting its interrupt priority level to 0. Each interrupt priority level > Processor interrupt priority level (IPL) Table 4.3.1 lists the setting of interrupt priority level, and Table 4.3.2 lists the interrupt enabled level corresponding to IPL contents. All the interrupt disable flag (I), interrupt request bit, interrupt priority level select bits, and processor interrupt priority level (IPL) are independent of one another; they do not affect one another. Interrupt requests are accepted only when the following conditions are satisfied. •Interrupt disable flag (I) = “0” •Interrupt request bit = “1” •Interrupt priority level > Processor interrupt priority level (IPL) 4.3 Interrupt control |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |