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7751 Datasheet(PDF) 33 Page - Renesas Technology Corp |
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7751 Datasheet(HTML) 33 Page - Renesas Technology Corp |
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33 / 540 page ![]() CENTRAL PROCESSING UNIT (CPU) 7751 Group User’s Manual 2–14 2.2 Bus interface unit (4) Bus control To perform the above operations (1) to (3), the BIU inputs and outputs the control signals, and controls the address bus and the data bus. The cycle in which the BIU controls the bus and accesses the memory•I/O device is called the bus cycle. Table 2.2.2 shows the bus cycle at accessing the internal area. Refer to “Chapter 12. CONNECTION WITH EXTERNAL DEVICES” about the bus cycle at accessing the external devices. Table 2.2.2 Bus cycle at accessing internal area RAM ROM SFR In low-speed running (f(XIN) ≤ 25 MHz) E Internal address bus Internal data bus Address Data 1 bus cycle = 3 1 bus cycle = 2 Address Internal address bus Internal data bus Data E Internal address bus Internal data bus 1 bus cycle = 2 Address Data E In high-speed running (f(XIN) ≤ 40 MHz) |
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