AD1937 datasheet(15/36 Pages) AD

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AD1937

Rev. 0 | Page 15 of 36

THEORY OF OPERATION

ANALOG-TO-DIGITAL CONVERTERS (ADCs)

There are four ADC channels in the AD1937 configured as two

stereo pairs with differential inputs. The ADCs can operate at a

nominal sample rate of 48 kHz, 96 kHz, or 192 kHz. The ADCs

include on-board digital antialiasing filters with 79 dB stop-

band attenuation and linear phase response, operating at an

oversampling ratio of 128 (48 kHz, 96 kHz, and 192 kHz modes).

Digital outputs are supplied through two serial data output

pins (one for each stereo pair): a common frame clock (ALRCLK)

and a common bit clock (ABCLK). Alternatively, the TDM

modes can be used to access up to 16 channels on a single

TDM data line.

The ADCs must be driven from a differential signal source for

best performance. The input pins of the ADCs connect to internal

switched capacitors. To isolate the external driving op amp from

the glitches caused by the internal switched capacitors, each

input pin should be isolated by using a series-connected external

100 Ω resistor and a 1 nF capacitor connected from each input

to ground. Use a high quality capacitor such as a ceramic

NP0/C0G, or polypropylene film.

The differential inputs have a nominal common-mode voltage

of 1.5 V. The voltage at the common-mode reference pin (CM)

can be used to bias external op amps to buffer the input signals

(see the Power Supply and Voltage Reference section). The

inputs can also be ac-coupled and in that case do not need

an external dc bias to CM.

A digital high-pass filter can be switched in line with the

ADCs (ADC Control 0 Register) to remove residual dc offsets.

It has a 1.4 Hz, 6 dB per octave cutoff at a 48 kHz sample rate.

The cutoff frequency scales directly with sample frequency.

DIGITAL-TO-ANALOG CONVERTERS (DACs)

The AD1937 DAC channels are arranged in four stereo pairs,

giving eight analog outputs; the outputs are differential for

improved noise and distortion performance. The DACs include

on-board digital reconstruction filters with 70 dB stop-band

attenuation and linear phase response, operating at an over-

sampling ratio of 4 (48 kHz or 96 kHz modes) or 2 (192 kHz

mode). Each channel has its own independently programmable

attenuator, adjustable in 255 steps in increments of 0.375 dB.

Digital inputs are supplied through four serial data input pins

(one for each stereo pair), a common frame clock (DLRCLK),

and a common bit clock (DBCLK). Alternatively, one of the

TDM modes can be used to access up to 16 channels on a

single TDM data line.

Each output pin has a nominal common-mode dc level of 1.5 V

and swings ±1.27 V for a 0 dBFS digital input signal. A single

op amp, third-order, external, low-pass filter is recommended

to remove high frequency noise present on the output pins, as

well as to provide a differential-to-single-ended conversion for

the differential output. Note that the use of op amps with low

slew rates or low bandwidth can cause high frequency noise

and tones to fold down into the audio band; exercise care in

selecting these components.

The voltage at CM can be used to bias the external op amps that

buffer the output signals (see the Power Supply and Voltage

Reference section).

CLOCK SIGNALS

The on-chip phase-locked loop (PLL) can be selected to ref-

erence the input sample rate from either of the LRCLK pins

or 256×, 384×, 512×, or 768× sample rate s (fS), referenced to

the 48 kHz mode from the MCLKI/MCLKXI pin. The default at

power-up is 256 × fS from the MCLKI/MCLKXI pin. In 96 kHz

mode, the master clock frequency stays at the same absolute

frequency; therefore, the actual multiplication rate is divided

by 2. In 192 kHz mode, the actual multiplication rate is divided

by 4. For example, if the AD1937 is programmed in 256 × fS

mode, the frequency of the master clock input is 256 × 48 kHz

= 12.288 MHz. If the AD1937 is then switched to 96 kHz

operation (by writing to the I2C port), the frequency of the

master clock should remain at 12.288 MHz, which is 128 × fS

in this example. In 192 kHz mode, this becomes 64 × fS.

The internal clock for the ADCs is 256 × fS for all clock modes.

The internal clock for the DACs varies by mode: 512 × fS (48 kHz

mode), 256 × fS (96 kHz mode), or 128 × fS (192 kHz mode). By

default, the on-board PLL generates this internal master clock

from an external clock. A direct 512 × fS (referenced to 48 kHz

mode) master clock can be used for either the ADCs or DACs,

if selected in the PLL and Clock Control 1 register.

Note that it is not possible to use a direct clock for the ADCs

set to the 192 kHz mode. It is required that the on-chip PLL

be used in this mode.

The PLL can be powered down in the PLL and Clock Control 0

or if the reference clock is unstable at power-on, power down

the PLL and then power it back up after the reference clock has

stabilized.

The internal master clock (MCLK) can be disabled in the

PLL and Clock Control 0 register to reduce power dissipation

when the AD1937 is idle. The clock should be stable before it

is enabled. Unless a standalone mode is selected (see the I2C

Control Port section), the clock is disabled by reset and must

be enabled by writing to the I2C port for normal operation.

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