AD1937

Rev. 0 | Page 26 of 36

ADDITIONAL MODES

The AD1937 offers several additional modes for board level

design enhancements. To reduce the EMI in board level design,

serial data can be transmitted without an explicit BCLK. See

Figure 28 and Figure 29 for an example of a DAC TDM data

transmission mode that does not require high speed DBCLK.

This configuration is applicable when the AD1937 master

clock is generated by the PLL with the DLRCLK as the PLL

reference frequency.

To relax the requirement for the setup time of the AD1937 in

cases of high speed TDM data transmission, the AD1937 can

latch in the data using the falling edge of DBCLK. This effec-

tively dedicates the entire BCLK period to the setup time. This

mode is useful in cases where the source has a large delay time

in the serial data driver. Figure 30 shows this pipeline mode of

data transmission.

Both the BCLK-less and pipeline modes are available on the

ADC serial data port.

DLRCLK

INTERNAL

DBCLK

DSDATAx

32 BITS

Figure 28. Serial DAC Data Transmission in TDM Format Without DBCLK; 2-Channel 64 BCLKs per Frame Mode

(Applicable Only If PLL Locks to DLRCLK; This Mode Is Also Available in the ADC Serial Data Port)

DLRCLK

DBCLK

DSDATAn

DATA MUST BE VALID

AT THIS BCLK EDGE

MSB

Figure 29. Serial DAC Data Transmission in TDM Format Without DBCLK; 128 to 512 BCLKs per Frame TDM Mode

(Applicable Only If PLL Locks to DLRCLK; This Mode Is Also Available in the ADC Serial Data Port)

DLRCLK

INTERNAL

DBCLK

TDM DSDATAn

(Applicable in Stereo and TDM, Useful for High Frequency TDM Transmission;

This Mode Is Also Available in the ADC Serial Data Port)