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AD1937 Datasheet(PDF) 29 Page - Analog Devices |
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AD1937 Datasheet(HTML) 29 Page - Analog Devices |
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29 / 36 page ![]() AD1937 Rev. 0 | Page 29 of 36 Table 25. DAC Control 1 Register (Address 3, 0x03) Bit Value Function Description 0 0 Latch in midcycle (normal) DBCLK active edge (TDM_IN) 1 Latch in at end of cycle (pipeline) 2:1 00 64 (2 channels) DBCLKs per frame 01 128 (4 channels) 10 256 (8 channels) 11 512 (16 channels) 3 0 Left low DLRCLK polarity 1 Left high 4 0 Slave DLRCLK master/slave 1 Master 5 0 Slave DBCLK master/slave 1 Master 6 0 DBCLK pin DBCLK source 1 Internally generated 7 0 Normal DBCLK polarity 1 Inverted Table 26. DAC Control 2 Register (Address 4, 0x04) Bit Value Function Description 0 0 Unmute Master mute 1 Mute 2:1 00 Flat De-emphasis (32 kHz/44.1 kHz/48 kHz mode only) 01 48 kHz curve 10 44.1 kHz curve 11 32 kHz curve 4:3 00 24 bits Word width 01 20 bits 10 Reserved 11 16 bits 5 0 Noninverted DAC output polarity 1 Inverted 7:6 00 Reserved Table 27. DAC Individual Channel Mutes Register (Address 5, 0x05) Bit Value Function Description 0 0 Unmute DAC1L mute 1 Mute 1 0 Unmute DAC1R mute 1 Mute 2 0 Unmute DAC2L mute 1 Mute 3 0 Unmute DAC2R mute 1 Mute 4 0 Unmute DAC3L mute 1 Mute 5 0 Unmute DAC3R mute 1 Mute 6 0 Unmute DAC4L mute 1 Mute 7 0 Unmute DAC4R mute 1 Mute |
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