AD1937 datasheet(28/36 Pages) AD

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AD1937

Rev. 0 | Page 28 of 36

Table 23. PLL and Clock Control 1 Register (Address 1, 0x01)

Bit

Value

Function

Description

PLL clock

DAC clock source select

MCLK

PLL clock

ADC clock source select

MCLK

Enabled

On-chip voltage reference

Disabled

Not locked

PLL lock indicator (read-only)

Locked

7:4

0000

Reserved

DAC CONTROL REGISTERS

Table 24. DAC Control 0 Register (Address 2, 0x02)

Bit

Value

Function

Description

Normal

Power-down

2:1

32 kHz/44.1 kHz/48 kHz

Sample rate

64 kHz/88.2 kHz/96 kHz

128 kHz/176.4 kHz/192 kHz

Reserved

5:3

000

1 cycle (I2S mode)

DSDATA delay (BCLK periods)

001

0 (left-justified mode)

010

8 cycles (right-justified 24-bit mode)

011

12 cycles (right-justified 20-bit mode)

100

16 cycles (right-justified 16-bit mode)

101

Reserved

110

Reserved

111

Reserved

7:6

Stereo (normal)

Serial format

TDM single-line, standalone, and daisy-chain modes

TDM/AUX mode (ADC-, DAC-, TDM-coupled)

TDM dual-line daisy-chain mode

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