ADF9010 datasheet(14/28 Pages) AD

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ADF9010

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LO Output

Mixers

The LOOUTP and LOOUTN pins are connected to the collectors

of an NPN differential pair driven by buffered outputs from the

VCO, as shown in Figure 18. To allow optimal power dissipation

vs. the output power requirements, the tail current of the diffe-

rential pair is programmable via Bit TP1 and Bit TP2 in the

control latch. The four current levels that can be set are: 6 mA,

8.5 mA, 11.5 mA, and 17.5 mA. These levels give output power

levels of −4 dBm, −1 dBm, +2 dBm, and +5 dBm, respectively,

if both outputs are combined in a 1 + 1:1 transformer or a 180°

microstrip coupler.

The ADF9010 has two double-balanced mixers, one for the

in-phase channel (I channel) and one for the quadrature

channel (Q channel). Both mixers are based on the Gilbert

cell design of four cross-connected transistors.

Tx Output

The TxOUTP and TxOUTN pins of the ADF9010 are connected

to the collectors of four NPN differential pairs driven by the

baseband signals, as shown in Figure 20. To allow the user

optimal power dissipation vs. the output power requirements,

the tail current of the differential pair is programmable via

Bit TP1 and Bit TP2 in the control latch. Two levels can be set;

these levels give output power levels of −3 dBm and, +3 dBm,

respectively, using a 50 Ω resistor to VDD and ac coupling into a

50 Ω load. Alternatively, both outputs can be combined in a 1 +

1:1 transformer or a 180° microstrip coupler. This buffer can be

powered off if desired.

If the outputs are used individually, the optimum output stage

consists of a shunt inductor to VDD.

Another feature of the ADF9010 is that the supply current to

the RF output stage is shut down until the part achieves lock as

measured by the digital lock detect circuitry. This is enabled by

the mute Tx until lock detect (F4) bit in the control latch.

VCO

LOOUTPLOOUTN

BUFFER/

DIVIDE BY 4

Another feature of the ADF9010 is that the supply current to the Tx

output stage is shut down until the part achieves lock as measured

by the digital lock detect circuitry. This is enabled by the mute LO

until lock detect bit (F5) in the control latch.

TxOUTP

TxOUTN

LOQP

LOQN

LOIP

LOIN

Figure 18. LO Output Section

Tx SECTION

Figure 20. Tx Section

TxOUTP

LOEXTP

LOEXTN

LOOUTP

LOOUTN

TxOUTN

TxBBQP

TxBBQN

TXBBIP

TXBBIN

÷4

QUAD

PHASE

SPLITTER

VCO

INT/

EXT

INTERFACING

Input Shift Register

The digital section of the ADF9010 includes a 24-bit input shift

rising edge of SCLK. The data is clocked in MSB first. Data is

transferred from the shift register to one of four latches on

the rising edge of SLE. The destination latch is determined by

the state of the two control bits (C2, C1) in the shift register.

These are the two LSBs, DB1 and DB0, as shown in Figure 21.

The truth table for Bit C3, Bit C2, and Bit C1 is shown in Table 7.

It displays a summary of how the latches are programmed. Note

that some bits are used for factory testing and should not be

programmed by the user.

Figure 19. Tx Section

Tx Baseband Inputs

Differential in-phase (I) and quadrature baseband (Q) inputs

are high impedance inputs that must be dc-biased to approx-

imately 500 mV dc and e driven from a low impedance source.

Nominal characterized ac signal swing is 700 mV p-p on each

pin. This results in a differential drive of 1.4 V p-p with a 500 mV

dc bias.

Table 7. Truth Table

Control Bits

Data Latch

Control latch

Tx latch

Rx calibration

LO latch

Rx filter

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