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ELECTRICAL CHARACTERISTICS

SWITCHING CHARACTERISTICS

TMDS361

www.ti.com............................................................................................................................................................................................ SLLS919 – DECEMBER 2008

over recommended operating conditions (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VOH

Single-ended HIGH-level output voltage

AVCC = 3.3 V, RT = 50 Ω

AVCC – 10

AVCC + 10

VOL

Single-ended LOW-level output voltage

AVCC – 600

AVCC – 400

VSWING

Single-ended output voltage swing

400

600

Change in steady-state common-mode

VOC(SS)

output voltage between logic states

VOD(pp)

Peak-to-peak output differential voltage

800

1200

V(O)SBY

Single-ended standby output voltage

AVCC – 10

AVCC + 10

0 V

≤ VCC ≤ 1.5 V, AVCC = 3.3 V,

I(O)OFF

Single-ended power-down output current

–10

µA

RT = 50 Ω

IOS

Short-circuit output current

See Figure 16

-15

VCD(pp)

Minimum valid clock differential voltage

Input TMDS clock frequency = 300

100

(peak-to-peak)

MHz

over recommended operating conditions (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP(1)

MAX

UNIT

tPLH

Propagation delay time

250

800

tPHL

Propagation delay time

250

800

tR1

Rise time, fastest mode (default setting):

110

140

Fastest Setting

tF1

Fall time, fastest mode (default setting):

110

140

Fastest Setting

tR2

Rise time, fastest mode + 50 ps

142

160

190

(approximately)

tF2

Fall time, fastest mode + 50 ps

142

160

190

AVCC = 3.3 V, RT = 50 Ω. See Figure 9 and

(approximately)

Figure 10.

tR3

Rise time, fastest mode + 100 ps

187

210

230

(approximately)

tF3

Fall time, fastest mode + 100 ps

187

210

230

(approximately)

tR4

Rise time, fastest mode + 120 ps

216

230

260

(approximately): Slowest Setting

tF4

Fall time, fastest mode + 120 ps

216

230

260

(approximately): Slowest Setting

tSK(P)

Pulse skew (see (2))

tSK(D)

Intra-pair skew

AVCC = 3.3 V, RT = 50 Ω. See Figure 11.

tSK(O)

Inter-pair skew (see (3))

100

tJITD(PP)

Peak-to-peak output residual data jitter

AVCC = 3.3 V, RT = 50 Ω, dR = 2.25 Gbps.

See Figure 14 for measurement setup;

residual jitter is the total jitter measured at

TTP4 minus the jitter measured at TTP1. See

Figure 15 for the loss profile of the cable used

for tJITD(PP) measurement. Also see Typical

Curves for tJITD(PP) across cable length and

input TMDS data rate.

(1)

All typical values are at 25°C and with a 3.3-V supply.

(2)

tsk(p) is the magnitude of the time difference between tPLH and tPHL of a specified terminal.

(3)

tsk(o) is the magnitude of the difference in propagation delay times between any specified terminals of a sink-port bank when inputs of

the active source port are tied together.

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