TMDS361 datasheet(23/42 Pages) TI

23 / 42 page

APPLICATION INFORMATION

Supply Voltage

TMDS Input Fail-Safe

TMDS Outputs

DDC I

2C Function Description

TMDS361

www.ti.com............................................................................................................................................................................................ SLLS919 – DECEMBER 2008

Table 3. TMDS361 vs TMDS351 Pinout

PIN NUMBER

I/O

TMDS351

TMDS361

Pins 32 and 33

GPIO mode: S1 and S2 configured as

GPIO mode: S1 and S2 configured as source selector pins (same as

source selector pins

TMDS351)

I2C mode: S1 and S2 configured as SCL and SDA for local slave I2C

communication

Pin 34

EQ: TMDS input equalization control

I2C_SEL: GPIO / local I2C control select

select

EQ = Low – HDMI 1.3 compliant cable

I2C_SEL = High – Device is configured by GPIO logic.

EQ = High – 10-m 28 AWG HDMI cable

I2C_SEL= Low – Device is configured by I2C logic.

Pin 49

—

VDD: HPD/DDC power supply

LP: Low-power mode select bar

LP = High – Normal operational mode

LP = Low – Device goes into low-power state.

Based on the differences listed in Table 3, attention must be given to pin 34, which determines whether the

device uses I2C or GPIO control.

The TMDS361 is powered up with a single power source that is 3.3-V VCC for the TMDS circuitry for HPD, DDC,

and most of the control logic.

The TMDS361 incorporates clock-detect circuitry. If there is no valid TMDS clock from the connected HDMI/DVI

source, the TMDS361 does not switch on the terminations on the source-side data channels. Additionally, the

TMDS outputs are placed in the high-impedance state. This prevents the TMDS361 from turning on its outputs if

there is no valid incoming HDMI/DVI data.

A 10% precision resistor, 4.02-k

Ω, is recommended to control the output swing to the HDMI-compliant 800-mV to

1200-mV range VOD(pp) (1000 mV typical). The TMDS outputs are high-impedance under standby mode

operation, S1 = H and S2 = L.

The TMDS361 provides buffers on the DDC I2C lines on all three input ports. This section explains the operation

of the buffer. For representation, the source side of the TMDS361 is represented by RSCL/RSDA, and the sink

side is represented by TSCL/TSDA. The buffers on the RSCL/RSDA and TSCL/TSDA pins are 5-V tolerant when

the device is powered off and high-impedance under low supply voltage, 1.5 V or below. If the device is powered

up, the driver T (see Figure 28) is turned on or off depending on the corresponding R-side voltage level.

When the R side is pulled low below 1.5 V, the corresponding T-side driver turns on and pulls the T side down to

a low level output voltage, VOL. The value of VOL and VIL on the T side or the sink side of the TMDS361 switch

depends on the output-voltage select (OVS) control settings. OVS control can be changed by the slave I2C, see

Table 8. When the OVS1 setting is selected, VOL is typically 0.7 V and VIL is typically 0.4 V. When the OVS2

setting is selected, VOL is typically 0.6 V and VIL is typically 0.4 V. When OVS3 setting (default) is selected, VOL is

typically 0.5 V and VIL is typically 0.3 V. VOL is always higher than the driver-R input threshold, VIL on the T side

or the sink side, preventing lockup of the repeater loop. The TMDS361 is targeted primarily as a switch in the

HDTV market and is expected to be a companion chip to an HDMI receiver; thus, the OVS control has been

provided on the sink side, so that the requirement of VIL to be less than 0.4 V can be met. The VOL value can be

selected to improve or optimize noise margins between VOL and VIL of the repeater itself or VIL of some external

device connected on the T side.

When the R side is pulled up, above 1.5 V, the T-side driver turns off and the T-side pin is high-impedance.

Submit Documentation Feedback

Product Folder Link(s) :TMDS361

TMDS361 Datasheet(PDF) 23 Page - Texas Instruments

TMDS361 Datasheet(HTML) 23 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42

Datasheet Download

Link URL