VREG5 Switch Over

VREG3 Switch Over

Powergood

Output Discharge Control

Low-Side Driver

High-Side Driver

TPS51123

When the VO1 voltage becomes higher than 4.7 V AND channel-1 internal powergood flag is generated, internal

5-V LDO regulator is shut off and the VREG5 output is connected to VO1 by internal switch over MOSFET. The

510-

µs powergood delay helps a switch over without glitch.

When the VO2 voltage becomes higher than 3.15 V AND channel-2 internal powergood flag is generated,

internal 3.3-V LDO regulator is shut off and the VREG3 output is connected to VO2 by internal switch over

MOSFET. The 510-

µs powergood delay helps a switch over without glitch.

The TPS51123 has one powergood output that indicates 'high' when both switcher outputs are within the targets

(AND gated). The powergood function is activated with 2-ms internal delay after ENC goes high. If the output

voltage becomes within ±5% of the target value, internal comparators detect power good state and the

powergood signal becomes high after 510-

µs internal delay. Therefore PGOOD goes high around 2.5 ms after

ENC goes high. If the output voltage goes outside of ±10% of the target value, the powergood signal becomes

low after 2-

µs internal delay. The powergood output is an open drain output and is needed to be pulled up

outside.

Also note that, in the case of Auto-skip or Out-of-Audio™ mode, if the output voltage goes +10% above the

target value and the power-good signal flags low, then the loop attempts to correct the output by turning on the

low-side driver (forced PWM mode). After the feedback voltage returns to be within +5% of the target value and

the power-good signal goes high, the controller returns back to auto-skip mode or Out-of-Audio™ mode.

When ENC is low, the TPS51123 discharges outputs using internal MOSFET which is connected to VOx and

GND. The current capability of these MOSFETs is limited to discharge slowly.

represented by its internal resistance, which are 4

Ω for VREG5 to DRVLx and 1.5 Ω for DRVLx to GND. A dead

time to prevent shoot through is internally generated between top MOSFET off to bottom MOSFET on, and

bottom MOSFET off to top MOSFET on. 5-V bias voltage is delivered from VREG5 supply. The instantaneous

drive current is supplied by an input capacitor connected between VREG5 and GND. The average drive current

is equal to the gate charge at Vgs = 5 V times switching frequency. This gate drive current as well as the

high-side gate drive current times 5 V makes the driving power which need to be dissipated from TPS51123

package.

floating driver, 5-V bias voltage is delivered from VREG5 supply. The average drive current is also calculated by

the gate charge at Vgs = 5 V times switching frequency. The instantaneous drive current is supplied by the flying

capacitor between VBSTx and LLx pins. The drive capability is represented by its internal resistance, which are 4

Ω for VBSTx to DRVHx and 1.5Ω for DRVHx to LLx.

Copyright © 2008, Texas Instruments Incorporated

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Product Folder Link(s): TPS51123