LPC2377 datasheet(18/55 Pages) NXP

18 / 55 page

LPC2377_78_4

Product data sheet

Rev. 04 — 19 November 2008

18 of 55

NXP Semiconductors

LPC2377/78

Single-chip 16-bit/32-bit microcontroller

FIQs have the highest priority. If more than one request is assigned to FIQ, the VIC ORs

the requests to produce the FIQ signal to the ARM processor. The fastest possible FIQ

latency is achieved when only one request is classiﬁed as FIQ, because then the FIQ

service routine can simply start dealing with that device. But if more than one request is

assigned to the FIQ class, the FIQ service routine can read a word from the VIC that

identiﬁes which FIQ source(s) is (are) requesting an interrupt.

Vectored IRQs, which include all interrupt requests that are not classiﬁed as FIQs, have a

programmable interrupt priority. When more than one interrupt is assigned the same

priority and occur simultaneously, the one connected to the lowest numbered VIC channel

will be serviced ﬁrst.

The VIC ORs the requests from all of the vectored IRQs to produce the IRQ signal to the

ARM processor. The IRQ service routine can start by reading a register from the VIC and

jumping to the address supplied by that register.

7.5.1 Interrupt sources

Each peripheral device has one interrupt line connected to the VIC but may have several

interrupt ﬂags. Individual interrupt ﬂags may also represent more than one interrupt

source.

Any pin on PORT0 and PORT2 (total of 46 pins) regardless of the selected function, can

be programmed to generate an interrupt on a rising edge, a falling edge, or both. Such

interrupt request coming from PORT0 and/or PORT2 will be combined with the EINT3

interrupt requests.

7.6 Pin connect block

The pin connect block allows selected pins of the microcontroller to have more than one

function. Conﬁguration registers control the multiplexers to allow connection between the

pin and the on chip peripherals.

Peripherals should be connected to the appropriate pins prior to being activated and prior

to any related interrupt(s) being enabled. Activity of any enabled peripheral function that is

not mapped to a related pin should be considered undeﬁned.

7.7 External memory controller

The LPC2377/78 EMC is an ARM PrimeCell MultiPort Memory Controller peripheral

offering support for asynchronous static memory devices such as RAM, ROM, and ﬂash.

In addition, it can be used as an interface with off-chip memory-mapped devices and

peripherals. The EMC is an Advanced Microcontroller Bus Architecture (AMBA) compliant

peripheral.

7.7.1 Features

• Asynchronous static memory device support including RAM, ROM, and ﬂash, with or

without asynchronous page mode

• Low transaction latency

• Read and write buffers to reduce latency and to improve performance

• 8 data and 16 address lines wide static memory support

• Two chip selects for static memory devices

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