LPC2377 datasheet(16/55 Pages) NXP

16 / 55 page

LPC2377_78_4

Product data sheet

Rev. 04 — 19 November 2008

16 of 55

NXP Semiconductors

LPC2377/78

Single-chip 16-bit/32-bit microcontroller

The key idea behind Thumb is that of a super-reduced instruction set. Essentially, the

ARM7TDMI-S processor has two instruction sets:

• the standard 32-bit ARM set

• a 16-bit Thumb set

The Thumb set’s 16-bit instruction length allows it to approach twice the density of

standard ARM code while retaining most of the ARM’s performance advantage over a

traditional 16-bit processor using 16-bit registers. This is possible because Thumb code

operates on the same 32-bit register set as ARM code.

Thumb code is able to provide up to 65 % of the code size of ARM, and 160 % of the

performance of an equivalent ARM processor connected to a 16-bit memory system.

7.2 On-chip ﬂash programming memory

The LPC2377/78 incorporates 512 kB ﬂash memory system. This memory may be used

for both code and data storage. Programming of the ﬂash memory may be accomplished

in several ways. It may be programmed In System via the serial port (UART0). The

application program may also erase and/or program the ﬂash while the application is

running, allowing a great degree of ﬂexibility for data storage ﬁeld and ﬁrmware upgrades.

The ﬂash memory is 128 bits wide and includes pre-fetching and buffering techniques to

allow it to operate at SRAM speeds of 72 MHz.

The LPC2377/78 provides a minimum of 100000 write/erase cycles and 20 years of data

retention.

7.3 On-chip SRAM

The LPC2377/78 includes a SRAM memory of 32 kB reserved for the ARM processor

exclusive use. This RAM may be used for code and/or data storage and may be accessed

as 8 bits, 16 bits, and 32 bits.

A 16 kB SRAM block serving as a buffer for the Ethernet controller and an 8 kB SRAM

used by the GPDMA controller or the USB device can be used for data and code storage.

The 2 kB RTC SRAM can be used for data storage only. The RTC SRAM is battery

powered and retains the content in the absence of the main power supply.

7.4 Memory map

The LPC2377/78 memory map incorporates several distinct regions as shown in Figure 3.

In addition, the CPU interrupt vectors may be remapped to allow them to reside in either

ﬂash memory (default), boot ROM, or SRAM (see Section 7.26.6).

LPC2377 Datasheet(PDF) 16 Page - NXP Semiconductors