LPC2377 datasheet(32/55 Pages) NXP

32 / 55 page

LPC2377_78_4

Product data sheet

Rev. 04 — 19 November 2008

32 of 55

NXP Semiconductors

LPC2377/78

Single-chip 16-bit/32-bit microcontroller

On the wake-up of power-down mode, if the IRC was used before entering power-down

mode, it will take IRC 60

µs to start-up. After this 4 IRC cycles will expire before the code

execution can then be resumed if the code was running from SRAM. In the meantime, the

ﬂash wake-up timer then counts 4 MHz IRC clock cycles to make the 100

µs ﬂash start-up

time. When it times out, access to the ﬂash will be allowed. The customers need to

reconﬁgure the PLL and clock dividers accordingly.

7.25.4.4

Power domains

The LPC2377/78 provides two independent power domains that allow the bulk of the

device to have power removed while maintaining operation of the RTC and the battery

RAM.

On the LPC2377/78, I/O pads are powered by the 3.3 V (VDD(3V3)) pins, while the

VDD(DCDC)(3V3) pin powers the on-chip DC-to-DC converter which in turn provides power to

the CPU and most of the peripherals.

Depending on the LPC2377/78 application, a design can use two power options to

manage power consumption.

The ﬁrst option assumes that power consumption is not a concern and the design ties the

VDD(3V3) and VDD(DCDC)(3V3) pins together. This approach requires only one 3.3 V power

supply for both pads, the CPU, and peripherals. While this solution is simple, it does not

support powering down the I/O pad ring “on the ﬂy” while keeping the CPU and

peripherals alive.

The second option uses two power supplies; a 3.3 V supply for the I/O pads (VDD(3V3)) and

a dedicated 3.3 V supply for the CPU (VDD(DCDC)(3V3)). Having the on-chip DC-to-DC

converter powered independently from the I/O pad ring enables shutting down of the I/O

pad power supply “on the ﬂy”, while the CPU and peripherals stay active.

The VBAT pin supplies power only to the RTC and the battery RAM. These two functions

require a minimum of power to operate, which can be supplied by an external battery.

When the CPU and the rest of chip functions are stopped and power removed, the RTC

can supply an alarm output that may be used by external hardware to restore chip power

and resume operation.

7.26 System control

7.26.1 Reset

Reset has four sources on the LPC2377/78: the RESET pin, the Watchdog reset,

power-on reset, and the BrownOut Detection (BOD) circuit. The RESET pin is a Schmitt

trigger input pin. Assertion of chip Reset by any source, once the operating voltage attains

a usable level, starts the Wake-up timer (see description in Section 7.25.3 “Wake-up

timer”), causing reset to remain asserted until the external Reset is de-asserted, the

oscillator is running, a ﬁxed number of clocks have passed, and the ﬂash controller has

completed its initialization.

When the internal Reset is removed, the processor begins executing at address 0, which

is initially the Reset vector mapped from the Boot Block. At that point, all of the processor

and peripheral registers have been initialized to predetermined values.

LPC2377 Datasheet(PDF) 32 Page - NXP Semiconductors

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