LPC2377 datasheet(20/55 Pages) NXP

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LPC2377_78_4

Product data sheet

Rev. 04 — 19 November 2008

20 of 55

NXP Semiconductors

LPC2377/78

Single-chip 16-bit/32-bit microcontroller

• An interrupt to the processor can be generated on a DMA completion or when a DMA

error has occurred.

• Interrupt masking. The DMA error and DMA terminal count interrupt requests can be

masked.

• Raw interrupt status. The DMA error and DMA count raw interrupt status can be read

prior to masking.

7.9 Fast general purpose parallel I/O

Device pins that are not connected to a speciﬁc peripheral function are controlled by the

GPIO registers. Pins may be dynamically conﬁgured as inputs or outputs. Separate

registers allow setting or clearing any number of outputs simultaneously. The value of the

output register may be read back as well as the current state of the port pins.

LPC2377/78 use accelerated GPIO functions:

• GPIO registers are relocated to the ARM local bus so that the fastest possible I/O

timing can be achieved.

• Mask registers allow treating sets of port bits as a group, leaving other bits

unchanged.

• All GPIO registers are byte and half-word addressable.

• Entire port value can be written in one instruction.

Additionally, any pin on PORT0 and PORT2 (total of 46 pins) providing a digital function

can be programmed to generate an interrupt on a rising edge, a falling edge, or both. The

edge detection is asynchronous, so it may operate when clocks are not present such as

during Power-down mode. Each enabled interrupt can be used to wake up the chip from

Power-down mode.

7.9.1 Features

• Bit level set and clear registers allow a single instruction to set or clear any number of

bits in one port.

• Direction control of individual bits.

• All I/O default to inputs after reset.

• Backward compatibility with other earlier devices is maintained with legacy PORT0

and PORT1 registers appearing at the original addresses on the APB bus.

7.10 Ethernet

The Ethernet block contains a full featured 10 Mbit/s or 100 Mbit/s Ethernet MAC

designed to provide optimized performance through the use of DMA hardware

acceleration. Features include a generous suite of control registers, half or full duplex

operation, ﬂow control, control frames, hardware acceleration for transmit retry, receive

packet ﬁltering and wake-up on LAN activity. Automatic frame transmission and reception

with scatter-gather DMA off-loads many operations from the CPU.

The Ethernet block and the CPU share a dedicated AHB subsystem that is used to access

the Ethernet SRAM for Ethernet data, control, and status information. All other AHB trafﬁc

in the LPC2377/78 takes place on a different AHB subsystem, effectively separating

Ethernet activity from the rest of the system. The Ethernet DMA can also access off-chip

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