LPC2387 datasheet(21/52 Pages) NXP

21 / 52 page

LPC2387_3

Product data sheet

Rev. 03 — 29 October 2008

21 of 52

NXP Semiconductors

LPC2387

Single-chip 16-bit/32-bit microcontroller

• Supports DMA transfers with the DMA RAM of 8 kB on all non-control endpoints.

• Allows dynamic switching between CPU-controlled and DMA modes.

• Double buffer implementation for Bulk and Isochronous endpoints.

7.10.2 USB host controller

The host controller enables full- and low-speed data exchange with USB devices attached

to the bus. It consists of register interface, serial interface engine, and DMA controller. The

OHCI speciﬁcation.

7.10.2.1

Features

• OHCI compliant.

• Two downstream ports.

• Supports per-port power switching.

7.10.3 USB OTG controller

USB OTG (On-The-Go) is a supplement to the USB 2.0 speciﬁcation that augments the

capability of existing mobile devices and USB peripherals by adding host functionality for

connection to USB peripherals.

The OTG Controller integrates the Host Controller, device controller, and a master-only

I2C interface to implement OTG dual-role device functionality. The dedicated I2C interface

controls an external OTG transceiver.

7.10.3.1

Features

• Fully compliant with On-The-Go supplement to the USB 2.0 Speciﬁcation, Revision

1.0a.

• Hardware support for Host Negotiation Protocol (HNP).

• Includes a programmable timer required for HNP and Session Request Protocol

(SRP).

• Supports any OTG transceiver compliant with the OTG Transceiver Speciﬁcation

(CEA-2011), Rev. 1.0.

7.11 CAN controller and acceptance ﬁlters

The Controller Area Network (CAN) is a serial communications protocol which efﬁciently

supports distributed real-time control with a very high level of security. Its domain of

application ranges from high-speed networks to low cost multiplex wiring.

The CAN block is intended to support multiple CAN buses simultaneously, allowing the

device to be used as a gateway, switch, or router among a number of CAN buses in

industrial or automotive applications.

Each CAN controller has a register structure similar to the NXP SJA1000 and the PeliCAN

Library block, but the 8-bit registers of those devices have been combined in 32-bit words

to allow simultaneous access in the ARM environment. The main operational difference is

that the recognition of received Identiﬁers, known in CAN terminology as Acceptance

Filtering, has been removed from the CAN controllers and centralized in a global

Acceptance Filter.

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