LPC2387 datasheet(23/52 Pages) NXP

23 / 52 page

LPC2387_3

Product data sheet

Rev. 03 — 29 October 2008

23 of 52

NXP Semiconductors

LPC2387

Single-chip 16-bit/32-bit microcontroller

7.14.1 Features

• 16 B Receive and Transmit FIFOs.

• Register locations conform to 16C550 industry standard.

• Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B.

• Built-in fractional baud rate generator covering wide range of baud rates without a

need for external crystals of particular values.

• Fractional divider for baud rate control, auto baud capabilities and FIFO control

mechanism that enables software ﬂow control implementation.

• UART1 equipped with standard modem interface signals. This module also provides

full support for hardware ﬂow control (auto-CTS/RTS).

• UART3 includes an IrDA mode to support infrared communication.

7.15 SPI serial I/O controller

The LPC2387 contains one SPI controller. SPI is a full duplex serial interface designed to

handle multiple masters and slaves connected to a given bus. Only a single master and a

single slave can communicate on the interface during a given data transfer. During a data

transfer the master always sends 8 bits to 16 bits of data to the slave, and the slave

always sends 8 bits to 16 bits of data to the master.

7.15.1 Features

• Compliant with SPI speciﬁcation

• Synchronous, serial, full duplex communication

• Combined SPI master and slave

• Maximum data bit rate of one eighth of the input clock rate

• 8 bits to 16 bits per transfer

7.16 SSP serial I/O controller

The LPC2387 contains two SSP controllers. The SSP controller is capable of operation on

a SPI, 4-wire SSI, or Microwire bus. It can interact with multiple masters and slaves on the

bus. Only a single master and a single slave can communicate on the bus during a given

data transfer. The SSP supports full duplex transfers, with frames of 4 bits to 16 bits of

data ﬂowing from the master to the slave and from the slave to the master. In practice,

often only one of these data ﬂows carries meaningful data.

7.16.1 Features

• Compatible with Motorola SPI, 4-wire Texas Instruments SSI, and National

Semiconductor Microwire buses

• Synchronous serial communication

• Master or slave operation

• 8-frame FIFOs for both transmit and receive

• 4-bit to 16-bit frame

• DMA transfers supported by GPDMA

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