LPC2387 datasheet(32/52 Pages) NXP

32 / 52 page

LPC2387_3

Product data sheet

Rev. 03 — 29 October 2008

32 of 52

NXP Semiconductors

LPC2387

Single-chip 16-bit/32-bit microcontroller

7.25.3 Code security (Code Read Protection - CRP)

This feature of the LPC2387 allows user to enable different levels of security in the system

so that access to the on-chip ﬂash and use of the JTAG and ISP can be restricted. When

needed, CRP is invoked by programming a speciﬁc pattern into a dedicated ﬂash location.

IAP commands are not affected by the CRP.

There are three levels of the Code Read Protection.

CRP1 disables access to chip via the JTAG and allows partial ﬂash update (excluding

ﬂash sector 0) using a limited set of the ISP commands. This mode is useful when CRP is

required and ﬂash ﬁeld updates are needed but all sectors can not be erased.

CRP2 disables access to chip via the JTAG and only allows full ﬂash erase and update

using a reduced set of the ISP commands.

Running an application with level CRP3 selected fully disables any access to chip via the

JTAG pins and the ISP. This mode effectively disables ISP override using P2[10] pin, too. It

is up to the user’s application to provide (if needed) ﬂash update mechanism using IAP

calls or call reinvoke ISP command to enable ﬂash update via UART0.

7.25.4 AHB

The LPC2387 implements two AHB in order to allow the Ethernet block to operate without

interference caused by other system activity. The primary AHB, referred to as AHB1,

includes the Vectored Interrupt Controller, GPDMA controller, USB interface, and 16 kB

SRAM primarily intended for use by the USB.

The second AHB, referred to as AHB2, includes only the Ethernet block and an

associated 16 kB SRAM. In addition, a bus bridge is provided that allows the secondary

AHB to be a bus master on AHB1, allowing expansion of Ethernet buffer space into

unused space in memory residing on AHB1.

In summary, bus masters with access to AHB1 are the ARM7 itself, the USB block, the

GPDMA function, and the Ethernet block (via the bus bridge from AHB2). Bus masters

with access to AHB2 are the ARM7 and the Ethernet block.

7.25.5 External interrupt inputs

The LPC2387 include up to 46 edge sensitive interrupt inputs combined with up to four

level sensitive external interrupt inputs as selectable pin functions. The external interrupt

inputs can optionally be used to wake up the processor from Power-down mode.

7.25.6 Memory mapping control

The memory mapping control alters the mapping of the interrupt vectors that appear at the

beginning at address 0x0000 0000. Vectors may be mapped to the bottom of the Boot

ROM or the SRAM. This allows code running in different memory spaces to have control

of the interrupts.

CAUTION

If level three Code Read Protection (CRP3) is selected, no future factory testing can be

performed on the device.

LPC2387 Datasheet(PDF) 32 Page - NXP Semiconductors

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